Method and system for processing a “WIDE” opcode when it is not used as a prefix for an immediately following opcode

• US 7,587,583 B2
• Filed: 07/25/2005
• Issued: 09/08/2009
• Est. Priority Date: 07/27/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Chauvel, Gerard
• Primary Examiner(s): Huisman; David J
• Application Number:
  US11/188,503
• Publication Number:
  US 20060026402A1
• Time in Patent Office: 1,506 Days
• Field of Search: 712/208, 712/210, 712/226, 712/229
• US Class Current: 712/226
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 2212/6012 of operating mode, e.g. cache mode or local memory mode
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/45504 Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and systems are provided for the selective use of a Java WIDE opcode as a prefix as defined in the instruction set of the Java virtual machine or performing a task assigned to the Java WIDE opcode. A Java WIDE opcode is fetched, a determination is made as to whether the Java WIDE opcode is to be used as a prefix, and when the Java WIDE opcode is not to be used as a prefix, a task assigned to the Java WIDE opcode is performed.

Claims

1. A method of operating a system including a stack machine and a processor that uses a stream of bytecodes for operation, the method comprising:

A. fetching a WIDE opcode from the stream of bytecodes;

B. determining whether the WIDE opcode is to be used as a prefix for an opcode that immediately follows the WIDE opcode in the stream of bytecodes; and

C. when the WIDE opcode is not to be used as a prefix, performing a task assigned to the WIDE opcode, the performing a task including;

i. using the WIDE opcode as an index into a vector table to locate an entry corresponding to the WIDE opcode;

ii. when a bit in the entry is asserted, initiating direct execution of the WIDE opcode; and

iii. when the bit in the entry is not asserted, triggering a micro-sequence referenced in the entry.

2. The method as defined in claim 1, wherein performing a task further comprises:

determining whether the WIDE opcode is directly executable or triggers a micro-sequence; and

when the WIDE opcode is directly executable, placing the WIDE opcode in a processor pipeline.

3. The method as defined in claim 2, further comprising:

when the WIDE opcode triggers the micro-sequence referenced in the entry,

changing the WIDE opcode to a NOP opcode,

executing the NOP opcode,

asserting a micro-sequence active bit, and

fetching a first instruction of the micro-sequence referenced in the entry.

4. The method as defined in claim 1, wherein determining whether the WIDE opcode is to be used as a prefix further comprises determining whether a flag in a register of the stack machine is asserted.

5. A processor comprising:

A. fetch logic configured to retrieve a WIDE opcode from a stream of bytecodes stored in a memory;

B. decode logic coupled to the fetch logic, wherein the decode logic is configured to;

i. determine, when the WIDE opcode is retrieved, whether the WIDE opcode is to be used as a prefix for an opcode that immediately follows the WIDE opcode in the stream of bytecodes; and

ii. when the WIDE opcode is not to be used as a prefix, cause performance of a task assigned to the WIDE opcode; and

C. a vector table accessible by the decode logic, the vector table including an entry corresponding to the WIDE opcode, the decode logic configured to cause performance of a task assigned to the WIDE opcode by;

i. using the WIDE opcode as an index into the vector table to locate the entry,

ii. initiating direct execution of the WIDE opcode when a bit in the entry is asserted, and

iii. triggering a micro-sequence referenced in the entry when the bit in the entry is not asserted.

6. The processor as defined in claim 5, wherein the decode logic is further configured to cause performance of a task assigned to the WIDE opcode by:

determining whether the WIDE opcode is directly executable or triggers a micro-sequence;

placing the WIDE opcode in a processor pipeline when the WIDE opcode is directly executable; and

placing a NOP opcode in the processor pipeline instead of the WIDE opcode when the WIDE opcode triggers the micro-sequence referenced in the entry.

7. A system comprising:

A. a first processor;

B. a memory coupled to the first processor, the memory configured to store a stream of bytecodes;

C. a second processor coupled to the first processor and the memory, the second processor including;

i. fetch logic configured to retrieve a WIDE opcode from the stream of bytecodes stored in the memory;

ii. decode logic coupled to the fetch logic, wherein the decode logic is configured to;

a. determine, when the WIDE opcode is retrieved, whether the WIDE opcode is to be used as a prefix for an opcode that immediately follows the WIDE opcode in the stream of bytecodes; and

b. when the WIDE opcode is not to be used as a prefix, cause performance of a task assigned to the WIDE opcode;

iii. a vector table coupled to and accessible by the decode logic, the vector table including an entry corresponding to the WIDE opcode; and

iv. wherein the decode logic is further configured to cause performance of a task assigned to the WIDE opcode by;

a. using the WIDE opcode as an index into the vector table to locate the entry,

b. initiating direct execution of the WIDE opcode when a bit in the entry is asserted, and

c. triggering a micro-sequence referenced in the entry when the bit in the entry is not asserted.

8. The system as defined in claim 7, wherein the decode logic is further configured to:

determine whether the WIDE opcode is directly executable or triggers a micro-sequence.

9. The processor as defined in claim 8, wherein the decode logic is further configured to cause performance of a task assigned to the WIDE opcode by:

placing the WIDE opcode in a processor pipeline when the WIDE opcode is directly executable; and

placing a NOP opcode in the processor pipeline instead of the WIDE opcode when the WIDE opcode triggers the micro-sequence referenced in the entry.