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Efficient front end memory arrangement to support parallel bit node and check node processing in LDPC (Low Density Parity Check) decoders

  • US 7,587,659 B2
  • Filed: 06/30/2005
  • Issued: 09/08/2009
  • Est. Priority Date: 05/31/2002
  • Status: Active Grant
First Claim
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1. A decoder that is operable to decode an LDPC (Low Density Parity Check) coded signal, the decoder comprising:

  • a controller that provides a modulation/code signal indicating at least one of a respective code rate and a respective modulation corresponding to each respective symbol of the LDPC coded signal, each symbol of the LDPC signal having a respective in-phase (I) value, a respective quadrature (Q) value, and a respective signal to noise ratio;

    a metric generator circuitry that includes a symbol metric calculator circuitry and a bit metric calculator circuitry, wherein;

    the symbol metric calculator circuitry, coupled to the controller, processes a respective symbol'"'"'s I value using a respective plurality of predetermined I coefficients and processes the respective symbol'"'"'s Q value using a respective plurality of predetermined Q coefficients selected based on the modulation/code signal thereby generating a plurality of symbol metrics corresponding to the respective symbol;

    the bit metric calculator circuitry, coupled to the symbol metric calculator circuitry and to the controller, includes a plurality of min* (min-star) processing circuitries, that processes the plurality of symbol metrics corresponding to the respective symbol thereby generating a respective plurality of bit metrics based on the modulation/code signal;

    a plurality of macro circuitries, coupled to the bit metric calculator circuitry, such that each of the plurality of macro circuitries includes;

    a corresponding metric memory that performs dual port memory management on respective pluralities of bit metrics; and

    a corresponding plurality of bit/check processor circuitries that employs at least one respective plurality of bit metrics to update bit edge messages and check edge messages; and

    a hard limiter, coupled to the plurality of macro circuitries, that generates a hard decision corresponding to at least one bit encoded within the LDPC coded signal based on a most recently updated plurality of bit edge messages.

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