Efficient front end memory arrangement to support parallel bit node and check node processing in LDPC (Low Density Parity Check) decoders
First Claim
1. A decoder that is operable to decode an LDPC (Low Density Parity Check) coded signal, the decoder comprising:
- a controller that provides a modulation/code signal indicating at least one of a respective code rate and a respective modulation corresponding to each respective symbol of the LDPC coded signal, each symbol of the LDPC signal having a respective in-phase (I) value, a respective quadrature (Q) value, and a respective signal to noise ratio;
a metric generator circuitry that includes a symbol metric calculator circuitry and a bit metric calculator circuitry, wherein;
the symbol metric calculator circuitry, coupled to the controller, processes a respective symbol'"'"'s I value using a respective plurality of predetermined I coefficients and processes the respective symbol'"'"'s Q value using a respective plurality of predetermined Q coefficients selected based on the modulation/code signal thereby generating a plurality of symbol metrics corresponding to the respective symbol;
the bit metric calculator circuitry, coupled to the symbol metric calculator circuitry and to the controller, includes a plurality of min* (min-star) processing circuitries, that processes the plurality of symbol metrics corresponding to the respective symbol thereby generating a respective plurality of bit metrics based on the modulation/code signal;
a plurality of macro circuitries, coupled to the bit metric calculator circuitry, such that each of the plurality of macro circuitries includes;
a corresponding metric memory that performs dual port memory management on respective pluralities of bit metrics; and
a corresponding plurality of bit/check processor circuitries that employs at least one respective plurality of bit metrics to update bit edge messages and check edge messages; and
a hard limiter, coupled to the plurality of macro circuitries, that generates a hard decision corresponding to at least one bit encoded within the LDPC coded signal based on a most recently updated plurality of bit edge messages.
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Abstract
Efficient front end memory arrangement to support parallel bit node and check node processing in LDPC (Low Density Parity Check) decoders. A novel approach is presented by which the front end design of device capable to decode LDPC coded signals facilitates parallel decoding processing of the LDPC coded signal. The implementation of the front end memory management in conjunction with the implementation of a metric generator operate cooperatively lend themselves for very efficient parallel decoding processing of LDPC coded signals. There are several embodiments by which the front end memory management and the metric generator may be implemented to facilitate this parallel decoding processing of LDPC coded signals. This also allows for the decoding of variable code rate and/or variable modulation signals whose code rate and/or modulation varies as frequently as on a block by block basis (e.g., a block may include a group of symbols within a frame).
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Citations
10 Claims
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1. A decoder that is operable to decode an LDPC (Low Density Parity Check) coded signal, the decoder comprising:
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a controller that provides a modulation/code signal indicating at least one of a respective code rate and a respective modulation corresponding to each respective symbol of the LDPC coded signal, each symbol of the LDPC signal having a respective in-phase (I) value, a respective quadrature (Q) value, and a respective signal to noise ratio; a metric generator circuitry that includes a symbol metric calculator circuitry and a bit metric calculator circuitry, wherein; the symbol metric calculator circuitry, coupled to the controller, processes a respective symbol'"'"'s I value using a respective plurality of predetermined I coefficients and processes the respective symbol'"'"'s Q value using a respective plurality of predetermined Q coefficients selected based on the modulation/code signal thereby generating a plurality of symbol metrics corresponding to the respective symbol; the bit metric calculator circuitry, coupled to the symbol metric calculator circuitry and to the controller, includes a plurality of min* (min-star) processing circuitries, that processes the plurality of symbol metrics corresponding to the respective symbol thereby generating a respective plurality of bit metrics based on the modulation/code signal; a plurality of macro circuitries, coupled to the bit metric calculator circuitry, such that each of the plurality of macro circuitries includes; a corresponding metric memory that performs dual port memory management on respective pluralities of bit metrics; and a corresponding plurality of bit/check processor circuitries that employs at least one respective plurality of bit metrics to update bit edge messages and check edge messages; and a hard limiter, coupled to the plurality of macro circuitries, that generates a hard decision corresponding to at least one bit encoded within the LDPC coded signal based on a most recently updated plurality of bit edge messages. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification