Operational time extension

• US 7,587,698 B1
• Filed: 05/21/2007
• Issued: 09/08/2009
• Est. Priority Date: 12/01/2004
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Rohe, Andre, Teig, Steven, Schmit, Herman, Redgrave, Jason, Caldwell, Andrew
• Primary Examiner(s): Tan, Vibol
• Assistant Examiner(s): WHITE, DYLAN C
• Application Number:
  US11/751,629
• Time in Patent Office: 841 Days
• Field of Search: 326 37- 41, 326/47, 716 1- 18
• US Class Current: 716/138
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: H03K 19/173 using elementary logic circuits as components
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17752 for hot reconfiguration
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration

Abstract

Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time.

Claims

1. A method of designing an integrated circuit (“

IC”

) with a plurality of configurable circuits that operate in a plurality of operational cycles, the method comprising;

a) assigning an operation on a signal path to a first operational cycle;

b) identifying that the assignment results in a violation of a timing constraint for the signal path; and

c) rectifying the violation by assigning the operation to both the first operational cycle and a second operational cycle subsequent to the first.

2. The method of claim 1, wherein a timing constraint is a specified length of time during which a particular set of operations must be performed.

3. The method of claim 2, wherein a violation of a timing constraint occurs when the particular set of operations cannot be performed in the specified length of time.

4. The method of claim 1 further comprising assigning a state element on the signal path to provide the same input to the operation in the first and second operational cycles.

5. A computer readable medium storing a computer program which when executed by at least one processor designs an integrated circuit (“

IC”

) with a plurality of configurable circuits that operate in a plurality of operational cycles, the computer program comprising sets of instructions for;

a) assigning an operation on a signal path to a first operational cycle;

b) identifying that the assignment results in a violation of a timing constraint for the signal path; and

c) rectifying the violation by assigning the operation to both the first operational cycle and a second operational cycle subsequent to the first.

6. The method of claim 5, wherein a timing constraint is a specified length of time during which a particular set of operations must be performed.

7. The method of claim 6, wherein a violation of a timing constraint occurs when the particular set of operations cannot be performed in the specified length of time.

8. The method of claim 5 further comprising assigning a state element on the signal path to provide the same input to the operation in the first and second operational cycles.