Controlling system for gate formation of semiconductor devices

• US 7,588,946 B2
• Filed: 07/25/2005
• Issued: 09/15/2009
• Est. Priority Date: 07/25/2005
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Su, Pin Chia, Hsu, Li Te, Wu, Mei-Jen, Tso, Chia-Tsung, Lai, Jiun-Hong, Chen, Po-Zen
• Primary Examiner(s): Smith; Matthew
• Assistant Examiner(s): Stark; Jarrett J
• Application Number:
  US11/188,324
• Publication Number:
  US 20070020777A1
• Time in Patent Office: 1,513 Days
• Field of Search: 438/5, 438/7, 438/12, 438/14, 438/16, 438/125, 438/9, 257/E21.528
• US Class Current: 438/9
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/26 Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement endpoint detection arrangements in CMP apparatus B24B37/013, in discharge apparatus H01J37/32
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of controlling gate formation of semiconductor devices includes determining the correlation between the step heights of isolation structures and the over-etching time by measuring step heights of isolation structures, determining an over-etching time based on the step heights, and etching gates using the over-etching time. The method may include an after-etching-inspection to measure the gate profile and fine-tune the gate formation control. Within-wafer uniformity can also be improved by measuring the step height uniformity on a wafer and adjusting gate formation processes.

Claims

1. A method of controlling gate formation of a semiconductor device, the method comprising:

measuring step heights between an isolation dielectric and an adjacent active region on wafers;

over-etching gates on the wafers and recording respective over-etching times;

measuring gate profiles of the gates, wherein the gate profiles are determined by measuring a difference between first widths of lower portions of the gates and respective second widths of upper portions of the gates;

determining a correlation between step heights and over-etching time using the step heights, the over-etching times, and the gate profiles;

measuring a step height of the semiconductor device on a target wafer;

determining an over-etching time based on the correlation and the step height of the semiconductor device on the target wafer; and

over-etching a target gate of the semiconductor device on the target wafer by feed forwarding the determined over-etching time.

2. The method of claim 1 wherein a gate electrode comprises polysilicon.

3. The method of claim 1 further comprising:

measuring the target gate profile after the etching the target gate; and

feeding back the target gate profile to the determining the over-etching time step.

4. The method of claim 1 further comprising determining a trimming time of a mask layer using the step height of the semiconductor device on the target wafer, wherein the mask layer is trimmed from a top and sides and wherein the mask layer is used for the over-etching the target gate of the semiconductor device on the target wafer.

5. The method of claim 4 further comprising:

performing an after-development-inspection of the mask layer to determine a critical dimension and a profile of the mask layer; and

feeding the critical dimension and the profile to the determining the trimming time step for over-etching a target gate of a next semiconductor device.

6. A method of controlling gate formation of a semiconductor device, the method comprising:

measuring a step height of a target wafer; and

determining a trimming time of a mask layer using the step height, wherein the mask layer is trimmed from a top and sides and wherein the mask layer is used for an over-etching a target gate of the semiconductor device of the target wafer.

7. The method of claim 6 further comprising:

measuring a critical dimension and measuring a profile of the mask layer in an after-development-inspection, wherein the profile of the mask layer is a relative width difference between a first width of a lower portion of the mask layer and a second width of an upper portion of the mask layer; and

feeding the critical dimension and the profile to the determining the trimming time step.

8. A method of controlling gate formation of a semiconductor device, the method comprising:

measuring a first step height of a first location and a second step height of a second location on a wafer;

determining non-uniformity of the wafer using the first and the second step heights; and

determining a gas injection mode for etching gates of MOS devices on the wafer that will substantially compensate for the non-uniformity of the wafer using the determined non-uniformity.

9. A method of forming a semiconductor device comprising:

consigning to a determination unit an optimized over-etch time for each of a plurality of step heights;

providing a step height, for a target wafer, to the determination unit, wherein the step height is obtained by measuring the step height between an isolation dielectric and an adjacent active region on the semiconductor device of the target wafer; and

performing an over-etch process on a gate structure of the semiconductor device of the target wafer, wherein an over-etch time is fed forward to the over-etch process by the determination unit.

10. The method of claim 9, wherein the optimized over-etch time is pre-determined by a process comprising:

storing a first step height measured on a first wafer;

etching a first gate structure on the first wafer using a first over-etch time;

determining and storing a first gate profile wherein the first gate profile is determined by measuring a difference between first widths of lower portions of the first gate structure and respective second widths of upper portions of the first gate structure;

storing a second step height measured on a second wafer;

etching a second gate structure on the second wafer using a second over-etch time;

measuring and storing a second gate profile wherein the second gate profile is determined by measuring a difference between first widths of lower portions of the second gate structure and respective second widths of upper portions of the second gate structure; and

construing an optimized plurality of over-etch times by predetermining a correlation between step height, over-etch time, and gate profile using the first gate profile, the second gate profile, the first over-etch time, the second over-etch time, the first step height and the second step height.

11. The method of claim 9, wherein the isolation dielectric is disposed in a shallow trench isolation (STI) structure.

12. The method of claim 9, wherein the gate structure comprises a polysilicon electrode.

13. The method of claim 9, wherein the step height is obtained by spectra critical dimension equipment.

14. The method of claim 9 further comprising:

performing an etch process on the gate structure prior to performing an over-etch process on the gate structure.

15. The method of claim 14, further comprising:

providing the determination unit with a gate profile of the gate structure following the etch process; and

dynamically selecting the over-etch time based on the gate profile provided.

16. The method of claim 9, further comprising:

forming a mask layer, wherein the mask layer is formed prior to performing the over-etch process;

implementing a trimming recipe, wherein the trimming recipe comprises a trim time; and

selecting the trim time based on the step height.

17. The method of claim 16, further comprising:

inspecting the mask layer following a development process to determine a critical dimension and a profile of the mask layer; and

providing the critical dimension and the profile of the mask layer to the determination unit to select the trim time.

18. The method of claim 9, further comprising:

providing a second step height, from a second location on the wafer, to the determination unit; and

determining a gas injection mode for the step of performing the over-etch process on the gate structure, based on a difference between the step height and the second step height.

19. The method of claim 9, wherein the determination unit consists of a unit selected from the group consisting of a unit integrated with a device dimension measuring system, a unit integrated with gate etching equipment, a separate fabrication operation system, a separate advanced process control (APC) system, or a combination thereof.

20. The method of claim 9 further comprising:

consigning to the determination unit an optimized trim time correlating to each of the plurality of step heights;

providing a second step height, for a second location on the wafer to the determination unit;

further providing a critical dimension of a mask layer;

executing a resist trim of the mask layer, wherein the determination unit provides the optimized trim time based on the step height and the critical dimension of the mask layer;

feeding back to the determination unit a post resist trim critical dimension of the mask layer and a post resist trim profile of the mask layer, wherein the determination unit, using the post resist trim critical dimension of the mask layer and the post resist trim profile of the mask layer, fine tunes the optimized trim time therein consigned;

determining a gas injection mode for the step of performing the over-etch process on the gate structure, based on a difference between the step height and the second step height; and

additionally feeding back to the determination unit a post etch gate profile, wherein the determination unit, using the post etch gate profile, fine tunes the optimized over-etch time therein consigned.