Test pattern for reliability measurement of copper interconnection line having moisture window and method for manufacturing the same

• US 7,588,950 B2
• Filed: 06/30/2004
• Issued: 09/15/2009
• Est. Priority Date: 11/18/2003
• Status: Active Grant

• Current Assignee: SK Keyfoundry Incorporated
• Original Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Inventors: Kim, Sang-Young
• Primary Examiner(s): Smith; Matthew
• Assistant Examiner(s): Jefferson; Quovaunda
• Application Number:
  US10/882,536
• Publication Number:
  US 20050106764A1
• Time in Patent Office: 1,903 Days
• Field of Search: 438/4, 438/14, 438/17, 438/18, 438/612, 438/618, 438/619, 438/622, 438/626, 438/627, 438/637, 438/638, 438/687, 438/688, 438/927, 438/FOR.101, 438/FOR.102, 438/FOR.358, 438/10, 438/11, 438/13, 438/FOR.142, 257/48, 257/E21.531, 257/E21.521, 257/E21.524, 257/E21.575, 257/E23.169, 257/758, 257/762, 257/773, 257/774, 702/117, 702/118, 73/73, 733/350.2, 733/350.5, 73/310.7, 324763-767, 324/769
• US Class Current: 438/18
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: G01R 31/2858 Measuring of material aspects, e.g. electro-migration [EM], hot carrier injection
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Disclosed is a test pattern for a reliability measurement of a copper interconnection line having a moisture window and a method for manufacturing the same. The method includes the steps of: a first inter-layer insulation layer formed on the substrate; a plurality of bottom copper interconnection lines buried in the first inter-layer insulation layer; a second inter-layer insulation layer on the plurality of bottom copper interconnection lines and the first inter-layer insulation layer; a plurality of top copper interconnection lines filled in the second inter-layer insulation layer and connected to the plurality of bottom copper interconnection lines through the plurality of via contacts; and a passivation layer covering the plurality of top copper interconnection lines and having a plurality of moisture windows in which moistures are flown during an electro migration (EM) test.

Claims

1. A method for fabricating a test pattern for reliability measurement of a copper interconnection line with a moisture window, comprising the steps of:

forming a trench inside a first inter-layer insulation layer on the substrate;

forming a second inter-layer insulation layer on a plurality of bottom copper interconnection lines and the first inter-layer insulation layer;

forming a plurality of top copper interconnection lines buried in the second inter-layer insulation layer through a dual damascene process and connected to the plurality of bottom copper interconnection lines through a plurality of via contacts; and

forming a plurality of passivation layers above the second inter-layer insulation layer and the plurality of top copper interconnection lines, each passivation layer having a width broader than a corresponding top copper interconnection line to cover the corresponding top copper interconnection line; and

forming a plurality of moisture windows between the plurality of passivation layers to open a top portion of the second inter-layer insulation layer allowing moisture to flow in through the second inter-layer insulation layer to flow into the top copper interconnection lines during an electro migration (EM) test,

wherein each of the plurality of moisture windows is a line shaped window opening a top portion of the second inter-layer insulation layer,

wherein the step of forming the passivation layer comprises the steps of;

forming the passivation layer covering the second inter-layer insulation layer and the plurality of top copper interconnection lines;

opening one side of the plurality of top copper interconnection lines by applying a pad etching process to the passivation layer;

forming a plurality of aluminum pads connected to the each corresponding top copper interconnection lines; and

forming a moisture window mask on the passivation layer and the plurality of aluminum pads.

2. The method of claim 1, wherein the moisture window is a line shaped window opening a top portion of the second inter-layer insulation layer in order to make the moisture flown in through the second inter-layer insulation layer to flow into the top copper interconnection line.

3. The method of claim 1, wherein the plurality of bottom copper interconnection lines and the plurality of top copper interconnection lines are surrounded by a diffusion barrier layer for preventing a diffusion of the copper atoms.