Method of packaging a semiconductor device and a prefabricated connector

• US 7,588,951 B2
• Filed: 11/17/2006
• Issued: 09/15/2009
• Est. Priority Date: 11/17/2006
• Status: Expired due to Fees

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Burch, Kenneth R., Mangrum, Marc A.
• Primary Examiner(s): Pham, Thanh V
• Application Number:
  US11/561,063
• Publication Number:
  US 20080119015A1
• Time in Patent Office: 1,033 Days
• Field of Search: 438/25, 438/26, 438/42, 438/43, 438/44, 438/51, 438/55, 438/64, 438/83, 438/98
• US Class Current: 438/25
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/8192 Applying permanent coating, e.g. protective coating
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/72 Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A method of packaging a first device having a first major surface and a second major surface includes forming a first layer over a second major surface of the first device and around sides of the first device and leaving the first major surface of the first device exposed, wherein the first layer is selected from the group consisting of an encapsulant and a polymer; forming a first dielectric layer over the first major surface of the first device, forming a via in the first dielectric layer, forming a seed layer within the via and over a portion of the first dielectric layer, physically coupling a connector to the seed layer, and plating a conductive material over the seed layer to form a first interconnect in the first via and over a portion of the first dielectric layer.

Claims

1. A method of packaging a first device having a first major surface (top) and a second major surface (bottom), comprising:

forming a first layer over the second major surface of the first device and around sides of the first device and leaving the first major surface of the first device exposed, wherein the first layer is selected from the group consisting of an encapsulant and a polymer;

forming a first dielectric layer over the first major surface of the first device;

forming a via in the first dielectric layer;

forming a seed layer within the via and over a portion of the first dielectric layer;

obtaining a prefabricated connector;

physically coupling the prefabricated connector having a contact portion to the seed layer; and

plating a conductive material over the seed layer to form a first interconnect in the via and over a portion of the first dielectric layer and around a portion of the contact portion of the prefabricated connector.

2. The method of claim 1, further comprising

forming a second dielectric layer over the first device before forming the first dielectric layer;

forming a second interconnect in the second dielectric layer, wherein the second interconnect is coupled to the first interconnect; and

forming a third interconnect in the second dielectric layer, wherein the third interconnect is coupled to an external connector.

3. The method of claim 2, wherein the external connection comprises solder balls.

4. The method of claim 2, wherein the external connector is formed over the first major surface of the first device and the connector is formed over the first major surface of the first device.

5. The method of claim 2, wherein the external connector is over the second major surface of the first device and the connector is formed over the first major surface of the first device.

6. The method of claim 1, wherein physically coupling a connector to the seed layer comprises placing the connector over the first major surface of the first device, wherein the first major surface of the first device comprises contacts.

7. The method of claim 1, wherein physically coupling a connector to the seed layer comprises placing the connector over the second major surface of the first device, wherein the first major surface of the first device comprises contacts.

8. The method of claim 1, wherein physically coupling a connector to the seed layer comprises:

placing the connector over the first layer, wherein;

the first layer comprises a first portion adjacent a second portion;

the first device is formed in the first portion of the first layer;

the connector is placed over the second portion of the first layer;

the connector comprises a side contact; and

the side contact is coupled to the seed layer.

9. The method of claim 8, wherein the side contact is selected from the group consisting of a female connector and a male connector.