Non-volatile memory devices including etching protection layers and methods of forming the same
First Claim
1. A non-volatile memory device, comprising:
- a semiconductor substrate including a cell array region and a peripheral circuit region;
a first cell unit on the semiconductor substrate in the cell array region;
a cell insulating layer on the first cell unit;
a first active body layer in the cell insulating layer and over the first cell unit;
a second cell unit on the first active body layer;
a peripheral transistor on the semiconductor substrate in the peripheral circuit region, the peripheral transistor having a gate pattern and source/drain regions;
a metal silicide layer on the gate pattern and/or on the source/drain regions of the peripheral transistor;
a peripheral insulating layer on the metal silicide layer and the peripheral transistor; and
an etching protection layer between the cell insulating layer and the peripheral insulating layer and between the metal silicide layer and the peripheral insulating layer.
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Accused Products
Abstract
A non-volatile memory device includes a semiconductor substrate including a cell array region and a peripheral circuit region. A first cell unit is on the semiconductor substrate in the cell array region, and a cell insulating layer is on the first cell unit. A first active body layer is in the cell insulating layer and over the first cell unit, and a second cell unit is on the first active body layer. The device further includes a peripheral transistor on the semiconductor substrate in the peripheral circuit region. The peripheral transistor has a gate pattern and source/drain regions, and a metal silicide layer is on the gate pattern and/or on the source/drain regions of the peripheral transistor. A peripheral insulating layer is on the metal silicide layer and the peripheral transistor, and an etching protection layer is between the cell insulating layer and the peripheral insulating layer and between the metal silicide layer and the peripheral insulating layer.
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Citations
21 Claims
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1. A non-volatile memory device, comprising:
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a semiconductor substrate including a cell array region and a peripheral circuit region; a first cell unit on the semiconductor substrate in the cell array region; a cell insulating layer on the first cell unit; a first active body layer in the cell insulating layer and over the first cell unit; a second cell unit on the first active body layer; a peripheral transistor on the semiconductor substrate in the peripheral circuit region, the peripheral transistor having a gate pattern and source/drain regions; a metal silicide layer on the gate pattern and/or on the source/drain regions of the peripheral transistor; a peripheral insulating layer on the metal silicide layer and the peripheral transistor; and an etching protection layer between the cell insulating layer and the peripheral insulating layer and between the metal silicide layer and the peripheral insulating layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of forming a non-volatile memory device, comprising:
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providing a semiconductor substrate having a cell array region and a peripheral circuit region; forming a first cell unit on the semiconductor substrate in the cell array region and a peripheral transistor on the semiconductor substrate in the peripheral region; forming a first insulating layer on the first cell unit and the peripheral transistor; forming a first active body layer on the first insulating layer in the cell array region; forming a second cell unit on the first active body layer; forming a second insulating layer on the second cell unit and the first insulating layer; patterning the first and second insulating layers to expose the peripheral transistor; forming a metal silicide layer on a gate pattern and/or on source/drain regions of the peripheral transistor; and forming a peripheral insulating layer on the metal silicide layer and the peripheral transistor. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification