Gate structure with low resistance for high power semiconductor devices
First Claim
1. A gate structure for a U-shape Metal-Oxide-Semiconductor (UMOS) device, comprising:
- a dielectric layer formed into a U-shape having side walls and a floor to form a trench surrounding a dielectric layer interior region;
a doped poly-silicon layer deposited adjacent to the dielectric layer within the dielectric layer interior region, the doped poly-silicon layer having side walls and a floor surrounding a doped poly-silicon layer interior region;
a first metal layer deposited adjacent to the doped poly-silicon layer and in the doped poly-silicon layer interior region on a side opposite from the dielectric layer, the first metal layer having side walls and a floor surrounding a first metal layer interior region; and
an undoped poly-silicon layer deposited to fill the first metal layer interior region, wherein;
the first metal layer is between the undoped poly-silicon layer and the doped poly-silicon layer; and
the undoped poly-silicon layer is interior to the doped poly-silicon layer.
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Abstract
In accordance with an embodiment of the present invention, a gate structure for a U-shape Metal-Oxide-Semiconductor (UMOS) device includes a dielectric layer formed into a U-shape having side walls and a floor to form a trench surrounding a dielectric layer interior region, a doped poly-silicon layer deposited adjacent to the dielectric layer within the dielectric layer interior region where the doped poly-silicon layer has side walls and a floor surrounding a doped poly-silicon layer interior region, a first metal layer deposited on the doped poly-silicon layer on a side opposite from the dielectric layer where the first metal layer has side walls and a floor surrounding a first metal layer interior region, and an undoped poly-silicon layer deposited to fill the first metal layer interior region.
20 Citations
18 Claims
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1. A gate structure for a U-shape Metal-Oxide-Semiconductor (UMOS) device, comprising:
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a dielectric layer formed into a U-shape having side walls and a floor to form a trench surrounding a dielectric layer interior region; a doped poly-silicon layer deposited adjacent to the dielectric layer within the dielectric layer interior region, the doped poly-silicon layer having side walls and a floor surrounding a doped poly-silicon layer interior region; a first metal layer deposited adjacent to the doped poly-silicon layer and in the doped poly-silicon layer interior region on a side opposite from the dielectric layer, the first metal layer having side walls and a floor surrounding a first metal layer interior region; and an undoped poly-silicon layer deposited to fill the first metal layer interior region, wherein; the first metal layer is between the undoped poly-silicon layer and the doped poly-silicon layer; and the undoped poly-silicon layer is interior to the doped poly-silicon layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A gate structure for a Junction Field Effect Transistor (JFET) device, comprising:
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a dielectric layer having two disjoint sidewall regions deposited on side walls of a trench having side walls and a floor, each disjoint side wall region having a first side facing into a trench interior region and a second side facing away from the trench interior region; a metal layer formed into a U-shape deposited on the dielectric layer first sides and the floor of the of the trench surrounding a metal layer interior region, the metal layer being electrically connected to a gate terminal; an undoped poly-silicon layer deposited to fill the metal layer interior region, the undoped poly-silicon layer being composed of a semiconductor material selected from the group consisting of silicon (Si) and silicon carbide (SiC). - View Dependent Claims (14, 15, 16, 17, 18)
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Specification