Semiconductor device and method of manufacturing the same

• US 7,589,388 B2
• Filed: 10/19/2007
• Issued: 09/15/2009
• Est. Priority Date: 10/23/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Semiconductor Company Limited (ON Semiconductor Corporation), Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Okada, Kazuo, Yamada, Hiroshi, Noma, Takashi, Morita, Yuichi, Kitagawa, Katsuhiko, Okubo, Noboru, Shinogi, Hiroyuki, Ishibe, Shinzo
• Primary Examiner(s): Zarneke; David A
• Assistant Examiner(s): Wagner; Jenny L
• Application Number:
  US11/875,438
• Publication Number:
  US 20080128914A1
• Time in Patent Office: 697 Days
• Field of Search: 257/433, 257/678, 257/690, 257/773, 257/779, 257/448, 257/457, 257/459
• US Class Current: 257/448
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/29101 the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/27 Manufacturing methods
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/30 of a plurality of layer connectors
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14683 Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10156 : at the periphery
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

The invention is directed to providing a package type semiconductor device with high reliability and smaller size and a method of manufacturing the same. A semiconductor substrate formed with a device element and a pad electrode on its front surface is prepared. The semiconductor substrate is then selectively etched from its back surface to form an opening. A second insulation film is then formed covering the side and back surfaces of the semiconductor substrate. First and second insulation films on the bottom of the opening are then selectively removed to expose a portion of the pad electrode. A wiring layer is then formed along the side surface of the semiconductor substrate, being electrically connected with the exposed pad electrode. An electrode connect layer is then formed covering the wiring layer. A protection layer is then formed covering the back surface of the semiconductor substrate and having an opening in a region for formation of a sidewall electrode. Then, the sidewall electrode is formed in a region exposed by the opening of the protection layer.

Claims

1. A semiconductor device comprising:

a semiconductor substrate comprising a front surface, a back surface and a side surface;

a device element formed on the front surface;

a pad electrode disposed on the front surface and electrically connected to the device element;

an insulation film covering the side surface and the back surface;

a wiring layer disposed on the side surface and electrically connected to the pad electrode;

a sidewall electrode disposed on the side surface so as to be electrically connected to the pad electrode through the wiring layer; and

a protection layer disposed on the back surface,

wherein the sidewall electrode is exposed along the side surface and accommodated in an opening formed in the protection layer.

2. The semiconductor device of claim 1, further comprising an electrode connect layer disposed between the sidewall electrode and the wiring layer, the electrode connect layer covering the wiring layer and electrically connecting the sidewall electrode and the wiring layer.

4. The semiconductor device of claim 1, wherein the wiring layer extends so as to cover a portion of the back surface.

3. The semiconductor device of claim l, further comprising a supporting body disposed on the front surface.