Charge pump circuit

• US 7,589,583 B2
• Filed: 11/13/2007
• Issued: 09/15/2009
• Est. Priority Date: 11/14/2006
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Semiconductor Company Limited (ON Semiconductor Corporation), Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Yoshikawa, Sadao, Rai, Toshiki
• Primary Examiner(s): ZWEIZIG, JEFFERY SHAWN
• Application Number:
  US11/939,388
• Publication Number:
  US 20080116961A1
• Time in Patent Office: 672 Days
• Field of Search: 327/535, 327/536, 327/537, 331/57
• US Class Current: 327/536
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type
• CPC Class Codes: H03K 3/0315 Ring oscillators

Abstract

The invention is mainly directed to providing a charge pump circuit which realizes low power consumption. A first clock signal is supplied from an oscillator circuit to capacitor elements forming a charge pump circuit. A current generation circuit controls a current flowing through each of inverters by controlling operation of PMOS and NMOS, and as a result controls the frequency of the first clock signal. A gate and a drain of PMOS are short-circuited, and between the node thereof and a ground terminal a constant current generation circuit and a resistor are connected in parallel. The constant current generation circuit serves to keep the current flowing through the inverters constant against a change of a power supply voltage. Therefore, the frequency of the clock signal is reduced according to the increase of the power supply voltage.

Claims

1. A charge pump circuit comprising:

a plurality of charge transfer devices connected in serial between an input terminal and an output terminal;

a plurality of capacitor elements, a terminal of each of the capacitor elements being connected to a corresponding connecting node of the charge transfer devices; and

an oscillator circuit connected to another terminal of said each of the capacitor elements and supplying a clock signal to the capacitor elements, the oscillator circuit comprising a ring oscillator circuit comprising a plurality of inverters and outputting the clock signal, and a current generation circuit controlling a current flowing through the inverters so as to reduce a frequency of the clock signal according to an increase of a power supply voltage,

wherein the ring oscillator circuit comprises first transistors controlling a current flowing from a power terminal to the inverters,

the current generation circuit comprises a second transistor forming a first current mirror circuit with the first transistors, a constant current generation circuit connected in serial with the second transistor and a resistor connected to the second transistor in parallel with the constant current generation circuit, and

the resistor has such a resistance value that a frequency of the clock signal is inversely proportional to an increase of a power supply voltage.

2. The charge pump circuit of claim 1, wherein the ring oscillator circuit further comprises a plurality of fourth transistors controlling a current flowing from the inverters to a ground terminal, and the current generation circuit further comprises a third transistor forming a second current mirror circuit with the second transistor and a fifth transistor connected in serial with the third transistor and forming a third current mirror circuit with the fourth transistors.