Fabric network management and diagnostic tool

• US 7,590,718 B2
• Filed: 07/26/2005
• Issued: 09/15/2009
• Est. Priority Date: 07/27/2004
• Status: Expired due to Fees

• Current Assignee: Fabric Embedded Tools Corporation
• Original Assignee: Fabric Embedded Tools Corporation
• Inventors: Parisien, Harvey, Gilmour, David Alexander
• Primary Examiner(s): Nguyen; Phuoc
• Application Number:
  US11/188,928
• Publication Number:
  US 20060026275A1
• Time in Patent Office: 1,512 Days
• Field of Search: 709223-238
• US Class Current: 709/223
• CPC Class Codes: H04L 41/12 Discovery or management of network topologies
• CPC Class Codes: H04L 41/22 comprising specially adapted graphical user interfaces [GUI]

Abstract

The invention relates to a maintenance and diagnostic tool for embedded fabric (EF) networks providing an interactive graphical user interface for displaying, monitoring and managing processing elements, such as microprocessors, switches, bridges and memory, within the EF network. The computer software tool identifies the various processing elements in the system along with the data routes therebetween, gives each processing element a unique identification label, and then initializes each switch with routing tables. All of the aforementioned information is then used to construct an interactive graphical user interface of the network map illustrating the various processing elements and the active and inactive data paths extending therebetween.

Claims

1. A method of creating an interactive network map for management of an embedded fabric based system including a plurality of processing elements, which include at lest one switch, comprising the steps of:

a) discovering processing elements in the system and data routes therebetween;

b) enumerating each processing element with a unique identification label;

c) initializing each switch with routing tables to ensure all processing elements are in communication with each other;

d) producing a graphical user interface including an interactive network map with corresponding icons for each processing element and the data routes therebetween utilizing information about the processing elements and data routes discovered in steps a), b), and c), whereby information about a specific processing element is displayed by activating the icon corresponding to the specific processing element; and

wherein step b) includes electronically placing a fingerprint in each processing element, whereby a same processing element is identifiable via multiple data routes enabling a system with multiple data routes to multiple processing elements to be mapped accordingly.

2. The method according to claim 1, wherein the processing elements include one or more selected from the group consisting of switches, bridges, memory and processors.

3. The method according to claim 2, wherein step a) includes accessing a library of known processing elements for detailed information relating to similar discovered processing elements.

4. The method according to claim 3, wherein step d) includes displaying processing elements found in the library in a format different than processing elements not found in the library.

5. The method according to claim 1, wherein step a) includes:

providing client software on a workstation connected to the system;

providing a server for a first processing element for communication with the client software; and

providing a driver for the first processing element for enabling communication between each server and the system.

6. The method according to claim 5, wherein step a) includes providing a server for a second processing element for communication with the client software;

wherein for step d) the client software reconciles network views from the first and second servers, whereby networks with many broken links are displayable in one composite view.

7. The method according to claim 1, wherein step b) includes automatically assigning the identification label to each processing element.

8. The method according to claim 1, wherein step b) includes prompting an operator for the identification label.

9. The method according to claim 1, wherein step b) includes creating annotations for each processing element comprising information relating to one or more of the characteristics selected from the group consisting of device type, device identification number, vendor identification number, number of ports, manufacturer, fault status, fault diagnosis, routing table status, and node identification label.

10. The method according to claim 1, wherein step d) includes displaying disabled data routes in a format different than enabled data routes.

11. The method according to claim 1, wherein step d) includes displaying disabled processing elements in a format different than enabled processing elements.

12. The method according to claim 1, wherein the embedded fabric based system is a system selected from the group consisting of a RapidIO system, a PCI Express system, and an Advanced Switching Interconnect system.

13. The method according to claim 1, further comprising establishing a link with at least one architectural register from one of the processing elements via the corresponding icon.

14. The method according to claim 13, further comprising automatically reestablishing the link with the at least one architectural register at desired time intervals.

15. The method according to claim 14, further comprising determining whether the one processing element is functioning properly from the at least one architectural register;

and providing a visual indication on the network map, when the one processing element fails to function properly.

16. The method according to claim 14, further comprising providing an alarm for providing an indication that the at least one register has an undesired value.

17. The method according to claim 14, further comprising producing a graph of network performance at various locations from information received from the at least one register.

18. The method according to claim 14, further comprising generating a report to support system design documentation or system diagnostics from information received from the at least one register.

19. The method according to claim 13, further comprising providing a user interface for editing the at least one register.

20. The method according to claim 1, wherein step d) includes providing an indication of forward and reverse routes between first and second processing elements, when the corresponding icons for the first and second processing elements are actuated;

and wherein the forward route is indicated by a different format than the reverse route, when the forward and reverse routes are different.

21. The method according to claim 20, wherein a new forward or reverse route between the first and second processing elements is capable of being generated by actuating, in sequence, the icon corresponding to the first processing element, all of the icons corresponding to processing elements between the first and second processing elements, and the second processing element.

22. The method according to claim 20, wherein a new forward or reverse route between the first and second processing elements is capable of being generated by actuating the first and second processing elements and an automatic routing function, which is based on desired criteria.

23. The method according to claim 1, wherein step d) includes attaching a PDF document to at least one processing element icon, whereby reference manual information is conveniently accessible.

24. The method according to claim 1, further comprising establishing a link with a desired switch in the network to determine routing table information;

wherein routing tables for the desired switch are displayable by activating an icon corresponding to the switch.

25. The method according to claim 1, wherein icons corresponding to at least one processing element are moveable on the network map, whereby the data routes to other processing elements move accordingly.

26. The method according to claim 1, wherein the processing elements includes at least one switch, at least one bridge, at least one memory and at least one processor.