Bulk data transfer and buffer control device and electronic instrument

• US 7,590,765 B2
• Filed: 01/25/2006
• Issued: 09/15/2009
• Est. Priority Date: 02/04/2005
• Status: Expired due to Fees

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Mikami, Yuji, Nagao, Kenyou, Oshita, Shun, Yanagihara, Shuichi
• Primary Examiner(s): Tsai; Henry W. H.
• Assistant Examiner(s): Nam; Hyun
• Application Number:
  US11/338,733
• Publication Number:
  US 20060179202A1
• Time in Patent Office: 1,329 Days
• Field of Search: 710/5, 710/100
• US Class Current: 710/5
• CPC Class Codes: G06F 13/12 using hardware independent of the central processor, e.g. channel or peripheral processor
• CPC Class Codes: G06F 13/426 using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus

Abstract

A data transfer control device for transferring data via a bus includes a buffer controller for controlling access to a data buffer in which a command block area, a data area and status block area are prepared, and a transfer controller for controlling data transfer. The transfer controller executes, a transaction of bulk OUT transfer in a command transport to automatically send a packet including command block data written in the command block area in response to an instruction to execute automatic bulk transfer, a transaction of one of bulk OUT transfer and bulk IN transfer in a data transport to automatically execute one of sending a packet including sending data written in the data area and receiving a packet including receiving data to be written in the data area, and a transaction of bulk IN transfer in a status transport to automatically receive a packet including status block data to be written in the status block area.

Claims

1. A data transfer control device that transfers data via a bus, comprising:

a buffer controller that controls access to a data buffer, the data buffer including a command block area, a data area and a status block area;

a transfer controller that controls data transfer;

a first circuit that instructs a commencement of a transaction of bulk OUT transfer in a command transport in response to an instruction on execution of the automatic bulk transfer;

a second circuit that selects either one of execution of a transaction of bulk OUT transfer in a data transport, execution of a transaction of bulk IN transfer in the data transport, or no execution of the data transport, based on information of a transfer direction of the data transport and information regarding presence or absence of the data transport in response to completion of the transaction of the bulk OUT transfer in the data transport commenced by the first circuit;

a third circuit that instructs a commencement of a transaction of the bulk OUT transfer in the data transport, and that instructs a commencement of a transaction of the bulk IN transfer in the data transport, in response to selection of executing the transaction of the bulk IN transfer in the data transport; and

a fourth circuit that instructs a commencement of a transaction of the bulk IN transfer in the command transport in response to completion of the bulk OUT transfer and the bulk IN transfer in the data transport;

the transfer controller executing the following transactions in the following order;

the transaction of the bulk OUT transfer in the command transport to automatically send a packet including command block data written in the command block area;

the transaction of one of the bulk OUT transfer and the bulk IN transfer in a data transport to automatically execute one of sending a packet including sending data written in the data area and receiving a packet including receiving data to be written in the data area; and

the transaction of the bulk IN transfer in a status transport to automatically receive a packet including status block data to be written in the status block area.

2. The data transfer control device according to claim 1, the transfer controller controlling a transaction of the data transport based on the command block data written in the command block area.

3. The data control device according to claim 2,

the transfer controller executing a transaction of the status transport omitting execution of a transaction of the data transport in accordance with a data transfer length of the command block data set to zero.

4. The data transfer control device according to claim 2, the transfer controller deciding, based on the command block data, which one of a transaction of the bulk OUT transfer and a transaction of the bulk IN transfer is executed in the data transport.

5. The data transfer control device according to claim 1, further comprising a channel information register to which channel information of a channel area prepared in the data buffer is set, the data area being prepared as the channel area, the channel information including a maximum packet size and a function address of a device,

the transfer controller executing the automatic bulk transfer based on the channel information set in the channel information register.

6. The data transfer control device according to claim 1, further comprising an automatic bulk transfer information register to which an OUT endpoint number designating an endpoint of the bulk OUT transfer and an IN endpoint number designating an endpoint of the bulk IN transfer are set as automatic bulk transfer information,

the transfer controller executing:

automatically sending a packet including the sending data to the endpoint designated by the OUT endpoint number if the transaction of the bulk OUT transfer is executed in the data transport, and automatically receiving a packet including the receiving data from the endpoint designated by the IN endpoint number if the transaction of the bulk IN transfer is executed in the data transport.

7. The data transfer control device according to claim 1, further comprising an analyzing circuit configured to analyze the status block data received in the status transport to detect an error in the status block data.

8. The data transfer control device according to claim 7, further comprising a processing section,

the analyzing circuit notifying the processing section of the error in the status block data if the error is detected in either of a plurality of fields of the status block data.

9. The data transfer control device according to claim 8, the processing section analyzing the status block data written in the status block area in response to the notification of the error in the status block data.

10. The data transfer control device according to claim 1, further comprising a processing section,

the transfer controller, upon detection of a transaction error in either one of the command transport, the data transport, and the status transport, stopping execution of the automatic bulk transfer and notifying the processing section of the transport in which the transaction error occurs.

11. The data transfer control device according to claim 1, further comprising:

a processing section,

the command block area including a first command block area and a second command block area, and

the transfer controller, while the processing section is writing the command block data to either one of the first and the second command block areas, executing the automatic bulk transfer based on the command block data written in the other of the first and the second command block areas.

12. The data transfer control device according to claim 1, the bus being a USB (Universal Serial Bus), and the command transport, the data transport, and the status transport being compliant to the bulk-only transport standard of the mass storage class.

13. An electronic instrument comprising:

the data transfer control device according to claim 1; and

a storage device storing data transferred by the data transfer control device.