Optimized switching method
First Claim
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1. A method comprising:
- receiving data units in the ingress portions of a plurality of port unitsa control matrix coupled to the port units performing prioritization, allocation, and virtual channel arbitration pursuant to a PCIE specification and setting a sequence in which the data units are sent to egress portions of the port units;
transferring data units to the egress portions of the port units in accordance with the sequence set by the control matrix; and
outputting data units from the egress portions of the port units,wherein the data units are not reordered after being transferred to the egress portions of the port units.
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Abstract
There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.
48 Citations
10 Claims
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1. A method comprising:
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receiving data units in the ingress portions of a plurality of port units a control matrix coupled to the port units performing prioritization, allocation, and virtual channel arbitration pursuant to a PCIE specification and setting a sequence in which the data units are sent to egress portions of the port units; transferring data units to the egress portions of the port units in accordance with the sequence set by the control matrix; and outputting data units from the egress portions of the port units, wherein the data units are not reordered after being transferred to the egress portions of the port units. - View Dependent Claims (2, 3, 4)
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5. A switch, comprising:
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a plurality of port units, each port unit having an ingress portion including an input queue and an egress portion; and a control matrix coupled between the plurality of port units, wherein the control matrix performs prioritization, allocation, and virtual channel arbitration pursuant to a PCI Express specification to determine the sequence in which data units are sent from the ingress portions of the port units to the egress portions of the port units, and wherein data units are not reordered after being sent to the egress portions of the port units. - View Dependent Claims (6, 7, 8, 9, 10)
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Specification