System and method for optimizing interconnections of components in a multichip memory module

• US 7,590,797 B2
• Filed: 04/08/2004
• Issued: 09/15/2009
• Est. Priority Date: 04/08/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Janzen, Jeffery W.
• Primary Examiner(s): Sough; Hyung S
• Assistant Examiner(s): Eland; Shawn
• Application Number:
  US10/822,275
• Publication Number:
  US 20050228939A1
• Time in Patent Office: 1,986 Days
• Field of Search: 711103-105, 711/115
• US Class Current: 711/105
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have approximately the same propagation time regardless of which device is involved. Specifically, the devices are arranged around the hub in pairs, with each pair of devices being oriented such that a functional group of signals for each device in the pair, such as the data bus signals, are positioned adjacent each other on a circuit board of the module. This allows for a data and control-address busses having approximately the same electrical characteristics to be routed between the hub and each of the devices. This physical arrangement of devices allows high speed operation of the module. In one example, the hub is located in the center of the module and eight devices, four pairs, are positioned around the hub.

Claims

1. A memory module comprising;

a circuit board;

a memory hub positioned on the circuit board;

a plurality of memory devices positioned around the memory hub and arranged in pairs on the same side of the circuit board as one another, each memory device having the same physical pin layout and including pins associated with a first functional group of signals adjacent a first end of each memory device and pins associated with a second functional group of signals adjacent a second end of each memory device, and the first end of each memory device in each pair being positioned adjacent one another on the circuit board and the second end of each device in a pair being positioned adjacent a second end of a device in one of the other pairs;

a plurality of command-address busses, each command-address bus coupled to a port on the memory hub and at least one of the pins associated with the second functional group of signals on each of the at least two memory devices, the two memory devices being from a different pair; and

an edge connector positioned along an edge of the circuit board and coupled to the memory hub.

2. The memory module of claim 1 wherein the first functional group of signals comprise data signals and the second functional group of signals comprise control-address signals.

3. The memory module of claim 1 wherein the memory devices comprise dynamic random access memories.

4. The memory module of claim 1 further comprising a second edge connector positioned along a second edge of the circuit boards and coupled to the memory hub.

5. The memory module of claim 1 wherein the module includes four pairs of devices, each pair being positioned adjacent a respective edge of the circuit board, and wherein the first functional group of signals comprise data signals and the second functional group of signals comprise control-address signals.

6. The memory module of claim 5 wherein the data signals of each memory device are carried on a data bus which is 9-bits wide.

7. The memory module of claim 1 wherein the module includes eight pairs of memory devices, four pairs positioned on a front side of the circuit board and four pairs positioned on a back side of the circuit board, each pair on the front side being positioned adjacent a corresponding pair on the back side, and wherein the eight pairs of memory devices comprise a single rank on the memory module.

8. The memory module of claim 7 wherein each of the memory devices includes a respective data bus, and wherein the respective data bus of half the memory devices are 4-bits wide and the respective data bus of the other half of the memory devices are 5 bits wide.

9. The memory module of claim 1 wherein the plurality of memory devices positioned around the memory hub are positioned on a front side of the circuit board, and wherein the memory module further comprises a second rank of memory devices positioned on a back side of the circuit board, each device on the back side being positioned adjacent a corresponding device on the front side.

10. A memory module comprising:

a circuit board;

a memory hub positioned on the circuit board;

a plurality of memory devices positioned around the memory hub and arranged in pairs on the same side of the circuit board as one another, each memory device having the same physical pin layout and where the pin layout includes pins associated with a first functional group of signals adjacent a first end of each memory device and pins associated with a second functional group of signals adjacent a second end of each memory device, and the first end of each memory device in each pair being positioned abutting one another on the circuit board;

a plurality of command-address busses, each command-address bus coupled to a port on the memory hub and at least one of the pins associated with the second functional group of signals on each of the at least two memory devices, the two memory devices being from a different pair; and

an edge connector positioned along an edge of the circuit board and coupled to the memory hub.

11. The memory module of claim 10 wherein the first functional group of signals comprise data signals and the second functional group of signals comprise control-address signals.

12. The memory module of claim 10 wherein the memory devices comprise dynamic random access memories.

13. The memory module of claim 10 further comprising a second edge connector positioned along a second edge of the circuit board and coupled to the memory hub.

14. The memory module of claim 10 wherein the module includes four pairs of devices, each pair being positioned perpendicular to adjacent pairs and located adjacent a respective edge of the circuit board, and wherein the first functional group of signals comprise data signals and the second functional group of signals comprise control-address signals.

15. The memory module of claim 14 wherein the data signals of each memory device are carried on a data bus which is 9-bits wide.

16. The memory module of claim 11 wherein the module includes a first pair of memory devices positioned adjacent a respective edge of the circuit board and a second pair positioned adjacent a diagonal opposite edge of the circuit board.

17. The memory module of claim 16 wherein the data signals of each memory device are carried on a data bus which is 18-bits wide.

18. The memory module of claim 10 wherein the module includes eight pairs of memory devices, four pairs positioned on a front side of the circuit board and four pairs positioned on a back side of the circuit board, each pair on the front side being positioned adjacent a corresponding pair on the back side, and wherein the eight pairs of memory devices comprise a single rank on the memory module.

19. The memory module of claim 18 wherein each of the memory devices includes a respective data bus, and wherein the respective data bus of half the memory devices are 4-bits wide and the respective data bus of the other half of the memory devices are 5 bits wide.

20. The memory module of claim 10 wherein the plurality of memory devices positioned around the memory hub are positioned on a front side of the circuit board, and wherein the memory module further comprises a second rank of memory devices positioned on a back side of the circuit board, each device on the back side being positioned adjacent a corresponding device on the front side.

21. A computer system, comprising:

a data input device;

a data output device;

a processor coupled to the data input and data output devices;

a controller electrically coupled to the processor, the controller being operable to receive and transmit memory signals on a high-speed data link;

at least one memory module coupled to the controller, each memory module comprising;

a circuit board;

a memory hub positioned on the circuit board;

a plurality of memory devices positioned around the memory hub and arranged in pairs on the same side of the circuit board as one another, each memory device having the same physical pin layout and including pins associated with a first functional group of signals adjacent a first end of each memory device and pins associated with a second functional group of signals adjacent a second end of each memory device, and the first end of each memory device in each pair being positioned abutting one another on the circuit board;

a plurality of command-address busses, each command-address bus coupled to a port on the memory hub and at least one of the pins associated with the second functional group of signals on each of the at least two memory devices, the two memory devices being from a different pair; and

an edge connector positioned along an edge of the circuit board and coupled to the memory hub.

22. The computer system of claim 21 wherein the memory devices comprise dynamic random access memories.

23. The computer system of claim 21 wherein the memory modules are coupled in a daisy chain manner to the controller.

24. The computer system of claim 21 wherein the high-speed data link comprises an optical communications link.

25. The computer system of claim 21 wherein on each memory module the plurality of memory devices positioned around the memory hub are positioned on a front side of the circuit board, and wherein the memory module further comprises a second rank of memory devices positioned on a back side of the circuit board, each device on the back side being positioned adjacent a corresponding device on the front side.

26. A method of forming a memory module including a circuit board, the method comprising:

positioning a memory hub on the circuit board;

positioning pairs of memory devices around the memory hub such that both devices in each pair are on the same side of the circuit board and each pair is perpendicular to adjacent pairs, each memory device in a respective pair being physically rotated 180 degrees in the plane of the circuit board relative to the other device in the pair;

coupling data signals between the memory hub and each memory device;

coupling control-address signals between a port on the memory hub and two memory devices via a common path, the two memory devices being from different pairs; and

routing a system bus to the memory hub.

27. The method of claim 26 wherein each memory device includes a pin 1 designated end and a first functional group of signals are adjacent this end of the device, and wherein the devices in each pair are positioned with the pin 1 designated ends abutting one another.

28. The method of claim 27 wherein the first functional group of signals comprises data bus signals.

29. The method of claim 26 wherein a data bus is routed between the hub and each device, and wherein signal lines of the data bus are routed parallel to edges of the circuit board.

30. The method of claim 26 wherein a control-address bus is routed between the hub and one device in each pair, and wherein signal lines of the control-address bus are routed diagonally outward from the hub towards corners of the circuit board.