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Mixed superscalar and VLIW instruction issuing and processing method and system

  • US 7,590,824 B2
  • Filed: 03/29/2005
  • Issued: 09/15/2009
  • Est. Priority Date: 03/29/2005
  • Status: Active Grant
First Claim
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1. A method for issuing and executing mixed architecture instructions at a multiple-issue digital signal processor, the method comprising:

  • receiving a mixed instruction listing including a plurality of digital signal processor instructions, said plurality of digital signal processor instructions comprising a plurality of parallel executable instructions mixed among a plurality of series executable instructions, said plurality of parallel executable instructions comprising a very long instruction word (VLIW) packet that includes VLIW instructions, said plurality of series executable instructions associated by various instruction dependencies;

    identifying in said mixed instruction listing said plurality of parallel executable instructions;

    executing in parallel said plurality of parallel executable instructions irrespective of the relative order of said parallel executable instructions in said mixed instruction listing; and

    executing serially said plurality of series executable instructions according to said various instruction dependencies after executing in parallel said plurality of parallel executable instructions.

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