Mixed superscalar and VLIW instruction issuing and processing method and system

• US 7,590,824 B2
• Filed: 03/29/2005
• Issued: 09/15/2009
• Est. Priority Date: 03/29/2005
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Anderson, William C., Codrescu, Lucian, Plondke, Erich, Ahmed, Muhammad
• Primary Examiner(s): Patel; Niketa I
• Assistant Examiner(s): Geib; Benjamin P
• Application Number:
  US11/093,375
• Publication Number:
  US 20060224862A1
• Time in Patent Office: 1,631 Days
• Field of Search: 712/23, 712/24, 712/214
• US Class Current: 712/214
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/3853 of compound instructions
• CPC Class Codes: G06F 9/3854 Instruction completion, e.g. retiring, committing or graduating
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory

Abstract

Techniques for processing transmissions in a communications (e.g., CDMA) system. A method and system for issuing and executing mixed architecture instructions in a multiple-issue digital signal processor receives in a mixed instruction listing a plurality of digital signal processor instructions. The plurality of digital signal processor instructions includes a plurality of parallel executable instructions (e.g., VLIW instructions or instruction packets) mixed among a plurality of series executable instructions (e.g., superscalar instructions). The series executable instructions are associated by various instruction dependencies. The method and system further identify in the mixed instruction listing the plurality of parallel executable instructions. Once identified, the parallel executable instructions are first executed in parallel irrespective of any such instruction'"'"'s relative order in the mixed instruction listing. Then, the series executable instructions are executed serially according to said various instruction dependencies.

Claims

1. A method for issuing and executing mixed architecture instructions at a multiple-issue digital signal processor, the method comprising:

receiving a mixed instruction listing including a plurality of digital signal processor instructions, said plurality of digital signal processor instructions comprising a plurality of parallel executable instructions mixed among a plurality of series executable instructions, said plurality of parallel executable instructions comprising a very long instruction word (VLIW) packet that includes VLIW instructions, said plurality of series executable instructions associated by various instruction dependencies;

identifying in said mixed instruction listing said plurality of parallel executable instructions;

executing in parallel said plurality of parallel executable instructions irrespective of the relative order of said parallel executable instructions in said mixed instruction listing; and

executing serially said plurality of series executable instructions according to said various instruction dependencies after executing in parallel said plurality of parallel executable instructions.

2. The method of claim 1, further comprising the step of executing superscalar instructions as said plurality of series executable instructions.

3. The method of claim 1, further comprising the step of executing said plurality of parallel executable instructions independent of performing a slot collision avoidance process on said plurality of digital signal processor instructions.

4. The method of claim 1, further comprising the step of detecting a read after write hazard among said plurality of series executable instructions.

5. The method of claim 1, further comprising the step of detecting a write after read hazard among said plurality of series executable instructions.

6. The method of claim 1, wherein said step of executing said plurality of parallel executable instructions further comprises the step of executing up to four parallel VLIW instructions in a single issue slot.

7. The method of claim 1, wherein said step of executing said plurality of parallel executable instructions further comprises the step of executing the VLIW packet, the VLIW packet comprising up to four VLIW instructions and one header instruction in a single issue slot.

8. The method of claim 1, wherein said step of executing said plurality of series executable instructions further comprises the step of executing up to five series executable instructions in a single issue slot.

9. An integrated circuit forming a portion of a digital signal processor for encoding and processing instructions of mixed lengths, the integrated circuit comprising:

an instruction unit operable to receive a mixed instruction listing including a plurality of digital signal processor instructions, said plurality of digital signal processor instructions comprising a plurality of parallel executable instructions including at least one very long instruction word (VLIW) packet having a packet header and at least one VLIW instruction mixed among a plurality of series executable instructions, said plurality of series executable instructions associated by various instruction dependencies;

a decode circuit operable to identify in said mixed instruction listing said plurality of parallel executable instructions;

a control circuit operable to execute in parallel said plurality of parallel executable instructions irrespective of the relative order of said plurality of parallel executable instructions in said mixed instruction listing and operable to execute serially said plurality of series executable instructions according to said various instruction dependencies after executing in parallel said plurality of parallel executable instructions.

10. The integrated circuit of claim 9, wherein said control circuit further comprises circuitry for executing the at least one VLIW instruction.

11. The integrated circuit of claim 9, wherein said control circuit further comprises circuitry for executing said plurality of parallel executable instructions independent of performing a slot collision avoidance process on said plurality of digital signal processor instructions.

12. The integrated circuit of claim 9, further comprising decoding and issue circuitry for detecting a read after write hazard among said plurality of series executable instructions.

13. The integrated circuit of claim 9, further comprising decoding and issue circuitry for detecting a write after read hazard among said plurality of series executable instructions.

14. The integrated circuit of claim 9, wherein said control circuit further comprises circuitry for executing up to four parallel VLIW instructions in a single issue slot.

15. The integrated circuit of claim 9, wherein said control circuit further comprises circuitry for executing the VLIW packet in a single issue slot, the VLIW packet comprising four VLIW instructions.

16. The integrated circuit of claim 9, wherein said control circuit further comprises circuitry for executing up to five series executable instructions in a single issue slot.

17. A digital signal processor for encoding and processing instructions of mixed lengths, the digital signal processor comprising:

means for receiving in a mixed instruction listing including a plurality of digital signal processor instructions, said plurality of digital signal processor instructions comprising a plurality of parallel executable instructions including at least one very long instruction word (VLIW) instruction packet mixed among a plurality of series executable instructions, the at least one VLIW instruction packet including multiple instructions determined by a compiler to be executable in parallel, said plurality of series executable instructions associated by various instruction dependencies;

means for identifying in said mixed instruction listing said plurality of parallel executable instructions;

means for executing in parallel said plurality of parallel executable instructions irrespective of the relative order of said plurality of parallel executable instructions in said mixed instruction listing; and

means for executing serially said plurality of series executable instructions according to said various instruction dependencies after executing in parallel said plurality of parallel executable instructions.

18. The digital signal processor of claim 17, wherein said executing means further comprises means for executing the at least one VLIW instruction packet.

19. The digital signal processor of claim 17, wherein said executing means further comprises means for executing superscalar instructions as said series executable instructions.

20. The digital signal processor of claim 17, wherein said executing means further comprises means for executing said plurality of parallel executable instructions independent of performing a slot collision avoidance process on said plurality of digital signal processor instructions.

21. The digital signal processor of claim 17, further comprising means for detecting at least one of a read after write hazard and a write after read hazard among said plurality of series executable instructions.

22. The digital signal processor of claim 17, wherein said executing means further comprises means for executing up to four parallel VLIW instructions in a single issue slot.

23. The digital signal processor of claim 17, wherein the VLIW packet includes up to four VLIW instructions and one header instruction.

24. A computer readable medium having computer readable instructions executable by a digital signal processor for encoding and processing instructions of mixed lengths, the computer readable instructions comprising instructions executable by the digital signal processor to:

receive a mixed instruction listing including a plurality of digital signal processor instructions, said plurality of digital signal processor instructions comprising a plurality of parallel executable instructions including at least one packetized very long instruction word (VLIW) instruction mixed among a plurality of series executable instructions, said plurality of series executable instructions associated by various instruction dependencies;

identify in said mixed instruction listing said plurality of parallel executable instructions;

execute in parallel said plurality of parallel executable instructions irrespective of the relative order of said plurality of parallel executable instructions in said mixed instruction listing; and

execute serially said plurality of series executable instructions according to said various instruction dependencies after executing in parallel said plurality of parallel executable instructions.

25. The computer readable medium of claim 24, further comprising computer readable instructions executable by the digital signal processor to execute the at least one packetized VLIW instruction.