Structured ASIC with configurable die size and selectable embedded functions

• US 7,590,967 B1
• Filed: 01/31/2007
• Issued: 09/15/2009
• Est. Priority Date: 06/04/2004
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Kirk, Robert S.
• Primary Examiner(s): Chiang; Jack
• Assistant Examiner(s): Tat; Binh C
• Application Number:
  US11/669,871
• Time in Patent Office: 958 Days
• Field of Search: 716 19- 21, 716/1, 716119-211
• US Class Current: 716/50
• CPC Class Codes: G03F 1/50 Mask blanks not covered by G03F1/20 - G03F1/34; Preparation thereof
• CPC Class Codes: G06F 2115/06 Structured ASICs
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00

Abstract

One embodiment of the present invention provides for a master or universal base and base tooling which addresses the general purpose Structured ASIC requirements. Another embodiment of the present invention provides for a common set of base tooling from which the master/universal base is created as well as additional custom bases with customized selection and quantity of embedded Platform ASIC functions. Embodiments can utilize conventional Structured ASIC architecture and processing and are compatible with traditional probing and packaging.

Claims

1. A method for customizing a wafer to implement customized applications, the method comprising:

an act of a machine accessing a multi-pattern base reticle field, the multi-pattern base reticle field having reticle tooling with a plurality of different individual die images, including at least a first individual die image and a second individual die image;

an act of the machine providing at least one base layer configured in a pattern of individual die, providing the pattern of individual die including;

an act of providing a first individual die image from the reticle tooling at a first one or more locations on the surface of a base wafer;

an act of providing a second different individual die image from the reticle tooling at a second one or more locations on the surface of the base wafer; and

an act of, subsequent to providing the individual die images, repeatedly providing a die cluster reticle field containing a group of one or more die clusters on top of an upper most base layer, the repeated providing of the die cluster reticle field containing a group of one or more die clusters resulting in a repeating pattern of die clusters on top of the pattern of individual die, each die cluster in the group of one or more die clusters grouping the resources of a corresponding one or more plurality of individual die contained in each die cluster and having one or more interconnections to the at least one base layer such that the resources of each die cluster can interoperate with resources in the corresponding grouping of individual die, wherein the act of repeatedly providing the die cluster reticle field is performed such that at least one die cluster in the group of one or more die clusters aligns with a first individual die provided from the first individual die image and a second individual die provided from a second individual die image to group the resources of the first individual die and the second individual die for implementing a customized application.

2. The method as recited in claim 1, wherein grouping the resources of the first individual die and the second individual die for implementing a customized application comprises grouping one or more resources are selected from among a logic gate, an I/O block, a memory, a timing generator, an I/O physical interface, and a processor.

3. The method as recited in claim 1, wherein the multi-pattern reticle comprises a multi-pattern reticle with a scribe line frame for surrounding one or more individual die.

4. The method as recited in claim 1, wherein the multi-pattern reticle comprises a multi-pattern reticle having one or more masked regions.

5. The method recited in claim 1, further comprising:

an act of defining a die cluster size that meets the resource requirements of a customized application.

6. The method recited in claim 1, further comprising:

an act of providing one or more additional different die images from the reticle tooling on the surface of the base wafer, each die image being printed at one or more corresponding locations on the surface of the base wafer.

7. The method recited in claim 1, wherein a boundary between the first and second die images comprised one or more scribe line regions including a guard ring that performs one or more of the following functions should the scribe line region be scribed:

1) protects the individual die from destructive effects of scribing,

     2) protects the edge of the individual die from cracking caused by scribing,

     3) protects the edge of the individual die from contaminates entering at the edge of the individual die,

     4) provides a common collection ring for stray currents that occur when the individual die is performing its operational functions.