Computer system

• US 7,590,990 B2
• Filed: 10/17/2005
• Issued: 09/15/2009
• Est. Priority Date: 11/24/2004
• Status: Expired due to Fees

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Kitamura, Akira, Asai, Noboru
• Primary Examiner(s): Truong; Lechi
• Application Number:
  US11/250,503
• Publication Number:
  US 20060112394A1
• Time in Patent Office: 1,429 Days
• Field of Search: 719/328, 710/48, 710/260, 718/328, 718/100, 714/10
• US Class Current: 719/328
• CPC Class Codes: G06F 9/45537 Provision of facilities of other operating environments, e.g. WINE I/O emulation G06F13/105

Abstract

A general-purpose OS (operating system) is used as a host OS and a real-time OS operating as one or more tasks on the host OS is used as a guest OS. An interrupt handler and a task on the host OS and an interrupt handler and a task on the guest OS issue APIs (application program interfaces) for requesting task state change to a start, stop or like state. An API processor is provided in each OS and outputs an instruction for task state change. An instruction storage for storing instructions output from an API processor of the guest OS in order and outputting the instructions is provided. When interrupt handlers are not in execution, an instruction synchronization timing controller preferentially selects from instructions output from the API processor of the host OS and from the instruction storage the latter and outputs the selected instruction to a scheduler.

Claims

1. A computer system comprising an OS (operating system) and a software component operating as one or more tasks running on the OS, the computer system further comprising:

a processor for executing said OS;

an OS interrupt handler and an OS task, each having a function of running on the OS and issuing an API (application program interface);

a first API processor having a function of outputting an instruction for changing a task state of the OS, based on an API issued by the OS interrupt handler and the OS task;

a second API processor having a function of outputting an instruction for changing a task state of the OS, based on an API for the software component;

an instruction storage for storing instructions output from the second API processor in order and outputting the instructions in the order that the instructions are stored;

an instruction synchronization timing controller for receiving an output of the first API processor and an output of the instruction storage as inputs, selecting, among the inputs, the instruction output from the instruction storage, and outputting the selected instruction;

a scheduler for processing the selected instruction output from the instruction synchronization timing controller, thereby selecting a task to be operated; and

a context switcher for executing task switching for the OS according to a selection made by the scheduler,

wherein the software component is a guest OS which operates, with the OS serving as a host OS, as one or more tasks running on the host OS,

wherein the computer system further includes a guest OS interrupt handler and a guest OS task, each having a function of running on the guest OS and issuing an API, and

wherein the second API processor has a function of outputting an instruction for changing a task state of the OS, based on an API issued by the guest OS interrupt handler and the guest OS task;

said computer system, further comprising;

a host OS interrupt state information output section for outputting as host OS interrupt state information whether or not a host OS interrupt handler for the OS interrupt handler is in execution; and

a guest OS interrupt state information output section for outputting as guest OS interrupt state information whether or not the guest OS interrupt handler is in execution,

wherein the instruction synchronization timing controller has a function of executing selection and outputting the selected instruction, based on the host OS interrupt state information and the guest OS interrupt state information at a timing in which neither the host OS interrupt handler nor the guest OS interrupt handler is in execution.

2. The computer system of claim 1, further comprising an interrupt state information controller for controlling effectiveness of each of the host OS interrupt state information and the guest OS interrupt state information,

wherein at least one of the first and second API processors has a function of outputting, when an API designating whether or not each of the host OS interrupt state information and the guest OS interrupt state information is invalidated, control information corresponding to the API to the interrupt state information controller, and

wherein if the host OS interrupt state information is invalidated, it is judged that the host OS interrupt handler is not in execution, and if the guest OS interrupt state information is invalidated, it is judged that the guest OS interrupt handler is not in execution.

3. A computer system comprising an OS (operating system) and a software component operating as one or more tasks running on the OS, the computer system further comprising:

a processor for executing said OS;

an OS interrupt handler and an OS task, each having a function of running on the OS and issuing an API (application program interface);

a first API processor having a function of outputting an instruction for changing a task state of the OS, based on an API issued by the OS interrupt handler and the OS task;

a second API processor having a function of outputting an instruction for changing a task state of the OS, based on an API for the software component;

an instruction storage for storing instructions output from the second API processor in order and outputting the instructions in the order that the instructions are stored;

an instruction synchronization timing controller for receiving an output of the first API processor and an output of the instruction storage as inputs, selecting, among the inputs, the instruction output from the instruction storage, and outputting the selected instruction;

a scheduler for processing the selected instruction output from the instruction synchronization timing controller, thereby selecting a task to be operated; and

a context switcher for executing task switching for the OS according to a selection made by the scheduler,

wherein the software component is a guest OS which operates, with the OS serving as a host OS, as one or more tasks running on the host OS,

wherein the computer system further includes a guest OS interrupt handler and a guest OS task, each having a function of running on the guest OS and issuing an API, and

wherein the second API processor has a function of outputting an instruction for changing a task state of the OS, based on an API issued by the guest OS interrupt handler and the guest OS task;

said computer system, further comprising;

another guest OS operating as one or more tasks running on the host OS;

another guest OS interrupt handler and another guest OS task, each having a function of operating on said another guest OS and issuing an API; and

a third API processor having a function of outputting an instruction for changing a task state of the host OS, based on an API issued by said another guest OS interrupt handler and said another guest OS task,

wherein the instruction storage has a function of receiving an output of the second API processor and an output of the third API processor as inputs and storing an instruction of one of the inputs.

4. The computer system of claim 3, further comprising a storage instruction selector for controlling, in the instruction storage, to which of the output of the second API processor and the output of the third API processor priority is given.

5. A computer system comprising an OS (operating system) and a software component operating as one or more tasks running on the OS, the computer system further comprising:

a processor for executing said OS;

an OS interrupt handler and an OS task, each having a function of running on the OS and issuing an API (application program interface);

a first API processor having a function of outputting an instruction for changing a task state of the OS, based on an API issued by the OS interrupt handler and the OS task;

a second API processor having a function of outputting an instruction for changing a task state of the OS, based on an API for the software component;

an instruction storage for storing instructions output from the second API processor in order and outputting the instructions in the order that the instructions are stored;

an instruction synchronization timing controller for receiving an output of the first API processor and an output of the instruction storage as inputs, selecting, among the inputs, the instruction output from the instruction storage, and outputting the selected instruction;

a scheduler for processing the selected instruction output from the instruction synchronization timing controller, thereby selecting a task to be operated; and

a context switcher for executing task switching for the OS according to a selection made by the scheduler,

wherein the software component is a guest OS which operates, with the OS serving as a host OS, as one or more tasks running on the host OS,

wherein the computer system further includes a guest OS interrupt handler and a guest OS task, each having a function of running on the guest OS and issuing an API, and

wherein the second API processor has a function of outputting an instruction for changing a task state of the OS, based on an API issued by the guest OS interrupt handler and the guest OS task

said computer system, further comprising;

another guest OS operating as one or more tasks running on the host OS;

another guest OS interrupt handler and another guest OS task, each having a function of operating on said another guest OS and issuing an API;

a third API processor having a function of outputting an instruction for changing a task state of the host OS, based on an API issued by said another guest OS interrupt handler and said another guest OS task; and

another instruction storage for storing instructions output from the second API processor and third API processor in order and outputting the instructions in the order that the instructions are stored,

wherein the instruction synchronization timing controller has a function of receiving an output of the instruction storage as well as an output of the first API processor and an output of said another instruction storage as inputs and outputting, among the inputs, an instruction output from the instruction storage or said another instruction storage.

6. The computer system of claim 5, further comprising a synchronization instruction selector for controlling, in the instruction synchronization timing controller, to which of an output of the instruction storage and an output of said another instruction storage priority is given.