Method of fabricating a storage device including decontinuous storage elements within and between trenches

• US 7,592,224 B2
• Filed: 03/30/2006
• Issued: 09/22/2009
• Est. Priority Date: 03/30/2006
• Status: Expired due to Fees

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Ingersoll, Paul A., Chindalore, Gowrishankar L., Swift, Craig T.
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US11/393,287
• Publication Number:
  US 20070238249A1
• Time in Patent Office: 1,272 Days
• Field of Search: 438/266, 438/259, 438/257, 438/260, 438/264, 257/E21.676
• US Class Current: 438/259
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 16/0458 comprising two or more independent floating gates which store independent data
• CPC Class Codes: G11C 2216/06 Floating gate cells in which the floating gate consists of multiple isolated silicon islands, e.g. nanocrystals
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor storage cell includes a first source/drain region underlying a first trench defined in a semiconductor layer. A second source/drain region underlies a second trench in the semiconductor layer. A first select gate in the first trench and a second select gate in the second trench are lined by a select gate dielectric. A charge storage stack overlies the select gates and a control gate overlies the stack. The DSEs may comprise discreet accumulations of polysilicon. An upper surface of the first and second select gates is lower than an upper surface of the first and second trenches. The control gate may be a continuous control gate traversing and running perpendicular to the select gates. The cell may include contacts to the semiconductor layer. The control gate may include a first control gate overlying the first select gate and a second control gate overlying the second select gate.

Claims

1. A method of fabricating a storage device in an array of storage cells, comprising:

forming first and second trenches in a semiconductor layer, wherein the first and second trenches are immediately adjacent trenches;

forming first and second source/drain regions underlying the first and second trenches, respectively;

forming first and second select gates in the first and second trenches, respectively;

forming a charge storage stack overlying the first and second select gates, wherein the charge storage stack includes a layer of discontinuous storage elements (DSEs), wherein, within a storage cell, a plurality of DSEs lies within at least one of the first and second trenches and over a first portion of the semiconductor layer between the first and second trenches;

forming a control gate overlying the charge storage layer; and

forming third source/drain regions that are spaced apart from each other and lie within second portions of the semiconductor layer between the first and second trenches.

2. The method of claim 1, wherein the DSEs comprise discrete accumulations of polysilicon.

3. The method of claim 1, further comprising lining the first and second trenches with a select gate dielectric prior to forming the first and second select gates.

4. The method of claim 3, wherein forming the first and second select gates comprises forming the first and second select gates wherein an upper surface of the first and second select gates is vertically displaced below an upper surface of the first and second trenches.

5. The method of claim 1, wherein forming the first and second select gates comprises forming the first and second select gates wherein an upper surface of the first and second select gates is vertically displaced below an upper surface of the first and second trenches.

6. The method of claim 5, wherein forming the control gate comprises forming a continuous control gate traversing the first and second trenches perpendicular to the first and second select gates.

7. The method of claim 5, wherein forming the control gate comprises forming a fist control gate overlying the first select gate and a second control gate overlying the second select gate.

8. The method of claim 1, wherein forming the control gate comprises forming a continuous control gate traversing the first and second trenches perpendicular to the first and second select gates.

9. The method of claim 8, further comprising forming first and second contacts to a semiconductor layer between the first and second trenches, wherein the first and second contacts are positioned on either side of the control gate between the first and second select gates.

10. The method of claim 9, wherein the DSEs comprise discrete accumulations of polysilicon.

11. The method of claim 9, further comprising lining the first and second trenches with a select gate dielectric prior to forming the first and second select gates.

12. The method of claim 9, wherein forming the first and second select gates comprises forming the first and second select gates wherein an upper surface of the first and second select gates is vertically displaced below an upper surface of the first and second trenches.

13. The method of claim 8, wherein forming the control gate comprises forming a first control gate overlying the first select gate and a second control gate overlying the second select gate.

14. The method of claim 1, wherein forming the control gate comprises forming a first control gate overlying the first select gate and a second control gate overlying the second select gate.

15. The method of claim 14, wherein lengths of the first and second control gates and lengths of the first and second select gates are parallel to one another.

16. The method of claim 14, wherein within a particular storage cell, the DSEs include a first injection region within the first trench and a second injection region within the second trench.

17. The method of claim 1, wherein each storage cell is configured to store more than one bit of datum.

18. The method of claim 1, wherein forming the third source/drain regions comprises forming the third source/drain regions spaced apart from walls of the first and second trenches.

19. The method of claim 1, wherein forming the third source/drain regions is performed after forming the control gate.

20. The method of claim 1, wherein within a particular storage cell, the DSEs include a first injection region within the first trench and a second injection region overlying the first portion of the semiconductor layer.