Semiconductor device having well with peak impurity concentrations and method for fabricating the same

• US 7,592,241 B2
• Filed: 12/22/2004
• Issued: 09/22/2009
• Est. Priority Date: 09/27/2004
• Status: Expired due to Fees

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Microelectronics Limited (Fujitsu Limited)
• Inventors: Takao, Yoshihiro
• Primary Examiner(s): Monbleau; Davienne
• Assistant Examiner(s): Trinh; Hoa B
• Application Number:
  US11/017,859
• Publication Number:
  US 20060071278A1
• Time in Patent Office: 1,735 Days
• Field of Search: 257/264, 257/348, 257402-407, 257/335, 257/E21.633, 257/E21.443, 257/497, 438231-232, 438/217, 438/224, 438/514, 438/543, 438/549, 438/527, 438/519, 438/545
• US Class Current: 438/514
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]

Abstract

The semiconductor device comprises a well 58 formed in a semiconductor substrate 10 and having a channel region; a gate electrode 34n formed over the channel region with an insulating film 32 interposed therebetween; source/drain regions 60 formed in the well 58 on both sides of the gate electrode 34n, sandwiching the channel region; and a pocket region 40 formed between the source/drain region and the channel region. The well 58 has a first peak of an impurity concentration at a depth deeper than the pocket region 40 and shallower than the bottom of the source/drain regions 60, and a second peak of the impurity concentration at a depth near the bottom of the source/drain regions 60.

Claims

1. A semiconductor device comprising:

a well of a first conductivity type formed in a semiconductor substrate and having a channel region;

a gate electrode formed over the channel region with an insulating film interposed therebetween;

source/drain regions of a second conductivity type formed in the well on both sides of the gate electrode, sandwiching the channel region; and

a pocket region of the first conductivity type formed between at least one of the source/drain regions and the channel region,

the well having a first peak of an impurity concentration of first impurities of the first conductivity type at a first depth deeper than the pocket region and shallower than the bottom of the source/drain regions, and a second peak of the impurity concentration of second impurities of the first conductivity type at a second depth near the bottom of the source/drain regions.

2. A semiconductor device according to claim 1, wherein

each of the source/drain regions includes a first impurity diffused region formed in alignment with the gate electrode, and a second impurity diffused region formed in alignment with a sidewall insulating film formed on the side wall of the gate electrode and being deeper than the first impurity diffused region, and

the pocket region is formed immediately below the first impurity diffused region.

3. A semiconductor device according to claim 1, wherein

the impurity concentration of the well at the second peak is higher than the impurity concentration of the well at the first peak.

4. A semiconductor device according to claim 1, wherein

the well has a third peak of the impurity concentration of third impurities of the first conductivity type at a third depth deeper than the source/drain regions.

5. A semiconductor device according to claim 4, wherein

the third peak is extended all over in the device isolation region.

6. A semiconductor device according to claim 1, wherein

the first impurity forming the first peak is mainly boron, and

the second impurity forming the second peak is mainly indium or gallium.

7. A semiconductor device according to claim 1, wherein

the first impurity forming the first peak is mainly phosphorus, and

the second impurity forming the second peak is mainly arsenic or antimony.

8. A semiconductor device according to claim 1, wherein

a gate length of the gate electrode is less than 60 nm.

13. A semiconductor device according to claim 1, wherein

the first peak is uniformly formed at the first depth uniformly throughout a region where the well is formed, and

the second peak is uniformly formed at the second depth throughout the region where the well is formed.

9. A semiconductor device including a logic unit and a memory unit, comprising:

a well of a first conductivity type formed in a semiconductor substrate of the logic unit and having a channel region; and

a logic transistor including a gate electrode formed over the channel region with an insulating film interposed therebetween, source/drain regions of a second conductivity type formed in the well on both sides of the gate electrode, sandwiching the channel region, and a pocket region of the first conductivity type formed between at least one of the source/drain regions and the channel region,

the well having a first peak of an impurity concentration of first impurities of the first conductivity type at a first depth deeper than the pocket region and shallower than the bottom of the source/drain regions, and a second peak of the impurity concentration of second impurities of the first conductivity type at a second depth near the bottom of the source/drain regions.

14. A semiconductor device according to claim 9, wherein

the first peak is uniformly formed at the first depth throughout a region where the well is formed, and

the second peak is uniformly formed at the second depth throughout the region where the well is formed.

10. A semiconductor device including a low-voltage transistor region and a high-voltage transistor region, comprising:

a well of a first conductivity type formed in a semiconductor substrate of the low-voltage transistor region and having a channel region; and

a low-voltage transistor including a gate electrode formed over the channel region with an insulating film interposed therebetween, source/drain regions of a second conductivity type formed in the well on both sides of the gate electrode, sandwiching the channel region, and a pocket region of the first conductivity type formed between at least one of the source/drain regions and the channel region,

the well having a first peak of an impurity concentration of first impurities of the first conductivity type at a first depth deeper than the pocket region and shallower than the bottom of the source/drain regions, and a second peak of the impurity concentration of second impurities of the first conductivity type at a second depth near the bottom of the source/drain regions.

15. A semiconductor device according to claim 10, wherein

the first peak is uniformly formed at the first depth throughout a region where the well is formed, and

the second peak is uniformly formed at the second depth throughout the region where the well is formed.

11. A method for fabricating a semiconductor device, including a well of a first conductivity type formed in a semiconductor substrate and having a channel region, a gate electrode formed over the channel region with an insulating film interposed therebetween, source/drain regions of a second conductivity type formed in the well on both sides of the gate electrode, sandwiching the channel region, and a pocket region of the first conductivity type formed between at least one of the source/drain regions and the channel region, the step of forming the well comprising the steps of:

forming a first impurity diffused region having a first peak of an impurity concentration of first impurities of the first conductivity type at a first depth deeper than the pocket region and shallower than the bottom of the source/drain regions; and

forming a second impurity diffused region having a second peak of the impurity concentration of second impurities of the first conductivity type at a second depth near the bottom of the source/drain regions.

12. A method for fabricating a semiconductor device according to claim 11, wherein

the step of forming the source/drain regions comprises the steps of:

implanting an impurity of the second conductivity type with the gate electrode as a mask to form a third impurity diffused region of the second conductivity type in the well at a depth shallower than the pocket region; and

implanting an impurity of the second conductivity type with the gate electrode and a sidewall insulating film formed on a side wall of the gate electrode as a mask to form a fourth impurity diffused region of the second conductivity type having a bottom positioned near the second peak.

16. A method for fabricating a semiconductor device according to claim 11, further comprising:

forming the gate electrode after forming the well having the first peak and the second peak.