Multilayer wiring board, manufacturing method thereof, semiconductor device, and wireless electronic device

• US 7,592,250 B2
• Filed: 01/16/2007
• Issued: 09/22/2009
• Est. Priority Date: 07/18/2002
• Status: Expired due to Fees

• Current Assignee: Hitachi Chemical Company Limited (Resonac Holdings Corp.)
• Original Assignee: Hitachi Chemical Company Limited (Resonac Holdings Corp.)
• Inventors: Hirata, Yoshitaka, Yamaguchi, Masanori, Otsuka, Kazuhisa, Shimayama, Yuichi, Kondou, Yuusuke, Mizushima, Etsuo, Madarame, Ken, Shimada, Yasushi, Kuriya, Hiroyuki, Yamamoto, Kazunori
• Primary Examiner(s): Dang; Phuc T
• Application Number:
  US11/653,417
• Publication Number:
  US 20070108588A1
• Time in Patent Office: 980 Days
• Field of Search: 438/622, 438/624, 438/625, 438/626, 257/691, 257/751, 257/754, 257/763, 257/E51.001, 257/E27.117, 257/E27.119
• US Class Current: 438/624
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 2201/0347 Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
• CPC Class Codes: H05K 2201/09509 Blind vias, i.e. vias having one side closed
• CPC Class Codes: H05K 2201/0959 Plated through-holes or plated blind vias filled with insulating material
• CPC Class Codes: H05K 3/4602 characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Abstract

A multilayer wiring board exhibiting excellent moldability and having a capacitor where variation of capacitance is suppressed, its producing method, a semiconductor device mounting a semiconductor chip on the multilayer wiring board, and a wireless electronic device mounting the semiconductor device.

Claims

1. A manufacturing method of a multilayer wiring board which includes a plurality of insulating layers, a plurality of conductive layers, a conductive non-through hole for electrically connecting the plurality of conductive layers to each other, and a capacitor produced by forming electrodes on upper and lower surfaces of at least one insulating layer containing a high-dielectric material, comprising at least:

the step of forming conductive patterns including one of the electrodes of the capacitor, the conductive patterns having a recessed portion between the conductive patterns;

the step of filling and hardening an insulating material different from the high-dielectric material in the recessed portion between the conductive patterns;

the step of planarizing the surfaces of the conductive patterns and the surface of the insulating material filled and hardened in the recessed portion between the conductive patterns by polishing, so as to form planarized surfaces of both the conductive patterns and the insulating material filled and hardened in the recessed portion between the conductive patterns;

the step of providing a high-dielectric material sheet in a semi-hardened state, said high-dielectric material sheet having the at least one insulating layer containing the high-dielectric material and a metal foil laminated thereto, and

the step of heating and laminating the high-dielectric material sheet in the semi-hardened state on the planarized surfaces of both the conductive patterns and the insulating material filled and hardened in the recessed portion, so that the at least one insulating layer of the high-dielectric material sheet is between (a) the conductive patterns and the insulating material filled and hardened in the recessed portion, and (b) the metal foil.

2. The manufacturing method of a multilayer wiring board according to claim 1, further comprising a step of forming a conductive pattern including another of the electrodes of the capacitor by etching the metal foil.

3. The manufacturing method of a multilayer wiring board according to claim 1, further comprising the step of forming an inductor in at least one of the conductive layers.

4. A semiconductor device wherein a semiconductor chip is mounted on a multilayer wiring board manufactured by a manufacturing method according to claim 1.

5. A wireless electronic device wherein a semiconductor device according to claim 4 is mounted.

6. The manufacturing method of a multilayer wiring board according to claim 1, wherein said recessed portion exposes an insulating structure underlying the conductive patterns, said insulating material being provided on the insulating structure.

7. The manufacturing method of a multilayer wiring board according to claim 1, wherein said conductive patterns are formed on an underlying substrate;

and, subsequent to forming the conductive patterns, the insulating material is filled and hardened in said recessed portions.

8. The manufacturing method of a multilayer wiring board according to claim 7, wherein said recessed portions expose the underlying substrate on which the conductive patterns are formed, and said insulating material is provided on the underlying substrate.