Charge balance techniques for power devices
First Claim
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1. A charge balance semiconductor power device, comprising:
- an active area comprising a plurality of cells capable of conducting current when biased in a conducting state;
a non-active perimeter region surrounding the active area, wherein no current flows through the non-active perimeter region when the plurality of cells are biased in the conducting state; and
alternately arranged strips of first conductivity type pillars and strips of second conductivity type pillars formed in a silicon region of the second conductivity type, the strips of first conductivity type pillars having a depth, a width and a length, the alternately arranged strips of first and second conductivity type extending along their length through both the active area and the non-active perimeter region, wherein each of the strips of first conductivity type pillars includes a discontinuity along its length forming a portion of a strip of second conductivity type region extending in the non-active perimeter region perpendicular to the strips of first conductivity type pillars.
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Abstract
A charge balance semiconductor power device includes an active area comprising a plurality of cells capable of conducting current when biased in a conducting state. A non-active perimeter region surrounds the active area, wherein no current flows through the non-active perimeter when the plurality of cells is biased in a conducting state. Alternately arranged strips of p pillars and strips of n pillars extend through both the active area and the non-active perimeter region along a length of a die housing the semiconductor power device.
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Citations
7 Claims
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1. A charge balance semiconductor power device, comprising:
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an active area comprising a plurality of cells capable of conducting current when biased in a conducting state; a non-active perimeter region surrounding the active area, wherein no current flows through the non-active perimeter region when the plurality of cells are biased in the conducting state; and alternately arranged strips of first conductivity type pillars and strips of second conductivity type pillars formed in a silicon region of the second conductivity type, the strips of first conductivity type pillars having a depth, a width and a length, the alternately arranged strips of first and second conductivity type extending along their length through both the active area and the non-active perimeter region, wherein each of the strips of first conductivity type pillars includes a discontinuity along its length forming a portion of a strip of second conductivity type region extending in the non-active perimeter region perpendicular to the strips of first conductivity type pillars. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification