Charge balance techniques for power devices

• US 7,592,668 B2
• Filed: 03/30/2006
• Issued: 09/22/2009
• Est. Priority Date: 03/30/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Kocon, Christopher Boguslaw
• Primary Examiner(s): Cao; Phat X
• Application Number:
  US11/396,239
• Publication Number:
  US 20070228490A1
• Time in Patent Office: 1,272 Days
• Field of Search: 257/335, 257/341
• US Class Current: 257/335
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A charge balance semiconductor power device includes an active area comprising a plurality of cells capable of conducting current when biased in a conducting state. A non-active perimeter region surrounds the active area, wherein no current flows through the non-active perimeter when the plurality of cells is biased in a conducting state. Alternately arranged strips of p pillars and strips of n pillars extend through both the active area and the non-active perimeter region along a length of a die housing the semiconductor power device.

Claims

1. A charge balance semiconductor power device, comprising:

an active area comprising a plurality of cells capable of conducting current when biased in a conducting state;

a non-active perimeter region surrounding the active area, wherein no current flows through the non-active perimeter region when the plurality of cells are biased in the conducting state; and

alternately arranged strips of first conductivity type pillars and strips of second conductivity type pillars formed in a silicon region of the second conductivity type, the strips of first conductivity type pillars having a depth, a width and a length, the alternately arranged strips of first and second conductivity type extending along their length through both the active area and the non-active perimeter region, wherein each of the strips of first conductivity type pillars includes a discontinuity along its length forming a portion of a strip of second conductivity type region extending in the non-active perimeter region perpendicular to the strips of first conductivity type pillars.

2. The charge balance semiconductor power device of claim 1 wherein each of the strips of first conductivity type pillars includes a plurality of discontinuities forming portions of a plurality of strips of second conductivity type regions extending in the non-active perimeter region perpendicular to the strips of first conductivity type pillars.

3. The charge balance semiconductor power device of claim 1 wherein the charge balance semiconductor power device is a vertically-conducting power device.

4. The charge balance semiconductor power device of claim 1 wherein the first conductivity type is p type and second conductivity type is n type.

5. The charge balance semiconductor power device of claim 1 further comprising a field plate in the non-active termination region.

6. The charge balance semiconductor power device of claim 1 wherein the non-active perimeter region comprises a plurality of rings of the first conductivity type extending around the active area.

7. The charge balance semiconductor power device of claim 1 further comprising a field plate conductor extending into the non-active perimeter region, wherein a portion of the field plate conductor is insulated from underlying strips of first conductivity type pillars and strips of second conductivity type pillars by a dielectric layer.