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Low leakage and data retention circuitry

  • US 7,592,837 B2
  • Filed: 09/19/2008
  • Issued: 09/22/2009
  • Est. Priority Date: 02/19/2004
  • Status: Active Grant
First Claim
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1. An integrated circuit comprising:

  • terminals including a common ground terminal and first and second power supply terminals;

    a level shifter configured to translate binary data from voltage levels defined by said first power supply terminal and said common ground terminal, to voltage levels defined by said second power supply terminal and said common ground terminal, said level shifter having a sleep transistor, input transistors, and cross-coupled output latching devices between said common ground terminal and an output terminal, said sleep transistor in series with an electrical connection to said common ground terminal, and said input transistors driven by inputs at voltage levels defined by said first power supply terminal and said common ground terminal; and

    power management circuitry configured to control power consumed by said level shifter using said sleep transistor.

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