Low leakage and data retention circuitry

• US 7,592,837 B2
• Filed: 09/19/2008
• Issued: 09/22/2009
• Est. Priority Date: 02/19/2004
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Mosaid Technologies Corporation (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Cole, Andrew, Callahan, John M., Walker, William G., Zampaglione, Michael A., Hoberman, Barry A., Hillman, Daniel L.
• Primary Examiner(s): Le; Don P
• Application Number:
  US12/284,311
• Publication Number:
  US 20090027080A1
• Time in Patent Office: 368 Days
• Field of Search: 326 63- 38, 326 80- 87
• US Class Current: 326/68
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/144 Detection of predetermined disconnection or reduction of power supply, e.g. power down or power standby
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 3/0372 of the master-slave type
• CPC Class Codes: H03K 3/356086 with additional means for controlling the main nodes H03K3/356104, H03K3/3562 take precedence
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit
• CPC Class Codes: H03K 5/14 by the use of delay lines H03K5/133 takes precedence

Abstract

An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

Claims

1. An integrated circuit comprising:

terminals including a common ground terminal and first and second power supply terminals;

a level shifter configured to translate binary data from voltage levels defined by said first power supply terminal and said common ground terminal, to voltage levels defined by said second power supply terminal and said common ground terminal, said level shifter having a sleep transistor, input transistors, and cross-coupled output latching devices between said common ground terminal and an output terminal, said sleep transistor in series with an electrical connection to said common ground terminal, and said input transistors driven by inputs at voltage levels defined by said first power supply terminal and said common ground terminal; and

power management circuitry configured to control power consumed by said level shifter using said sleep transistor.

2. The integrated circuit as claimed in claim 1 wherein said second power supply terminal provides a higher voltage than said first power supply terminal.

3. The integrated circuit as claimed in claim 1 wherein said level shifter is built into an input/output pad cell configured to interface with chip core logic.

4. The integrated circuit as claimed in claim 1 wherein said sleep transistor enables a power down mode.

5. The integrated circuit as claimed in claim 4 wherein said sleep transistor is an n-channel transistor connected to said common ground terminal.

6. The integrated circuit as claimed in claim 5 wherein said power management circuit applies a voltage from said first power supply terminal to said sleep transistor when not in said power down mode.

7. The integrated circuit as claimed in claim 5 wherein said power management circuit applies a voltage lower than a voltage level of said common ground terminal to said sleep transistor in said power down mode.

8. The integrated circuit as claimed in claim 5 wherein said power management circuit applies a voltage greater than a voltage level of said first power supply terminal to said sleep transistor when not in said power down mode.

9. The integrated circuit as claimed in claim 4 wherein said level shifter retains data in said power down mode.

10. The integrated circuit as claimed in claim 1 wherein said level shifter latches level shifted data.

11. The integrated circuit as claimed in claim 1 wherein said level shifter input transistors are thin gate transistors.

12. The integrated circuit as claimed in claim 1 wherein said level shifter comprises cross-coupled cascode devices.

13. The integrated circuit as claimed in claim 12 wherein said input transistors are thin gate transistors and said cross-coupled output latching devices comprise thick gate transistors.

14. The integrated circuit as claimed in claim 12 further comprising a static random access memory (SRAM) cell built into an output stage of said level shifter.

15. The integrated circuit as claimed in claim 14 further comprising an inverter to prevent inputs of said level shifter from reaching a voltage of said first power supply terminal at the same time.

16. The integrated circuit as claimed in claim 14 wherein said input transistors are configured to withstand voltages higher than that of said first power supply terminal.

17. A method for operating an integrated circuit, the method comprising:

providing first and second power supply terminals;

translating binary data with a level shifter from voltage levels defined by said first power supply terminal and a common ground terminal to voltage levels defined by said second power supply and said common ground terminal;

driving level shifter input transistors with voltage levels defined by said first power supply terminal and said common ground terminal; and

in a power down mode, controlling power consumed by said level shifter with a sleep transistor while said level shifter retains data.

18. The method as claimed in claim 17 wherein said second power supply terminal provides a higher voltage than said first power supply terminal.

19. The method as claimed in claim 17 further comprising preventing inputs of said level shifter from reaching the voltage level of said first power supply terminal at the same time.

20. The method as claimed in claim 17 further comprising latching level shifted data.

21. The method as claimed in claim 17 wherein controlling power consumed by said level shifter includes enabling a power down mode.

22. The method as claimed in claim 21 further comprising applying voltage from said first power supply terminal to said sleep transistor when not in said power down mode.

23. The method as claimed in claim 21 further comprising applying a voltage lower than that of said common ground terminal to said sleep transistor in said power down mode.

24. The method as claimed in claim 21 further comprising applying a voltage greater than the voltage level of said first power supply terminal to said sleep transistor when not in said power down mode.

25. The method as claimed in claim 21 further comprising retaining data with said level shifter in said power down mode.

26. An integrated circuit comprising:

terminals including a common ground terminal and first and second power supply terminals;

a level shifter built into an input/output pad cell configured to interface with chip core logic, said level shifter configured to translate binary data from voltage levels defined by said first power supply terminal and said common ground terminal, to voltage levels defined by said second power supply terminal and said common ground terminal, said level shifter having a sleep transistor and input transistors, said sleep transistor in series with an electrical connection to said common ground terminal, and said input transistors driven by inputs at voltage levels defined by said first power supply terminal and said common ground terminal; and

power management circuitry configured to control power consumed by said level shifter using said sleep transistor.

27. The integrated circuit as claimed in claim 26 wherein said second power supply terminal provides a higher voltage than said first power supply terminal.

28. The integrated circuit as claimed in claim 26 wherein said sleep transistor enables a power down mode.

29. The integrated circuit as claimed in claim 28 wherein said sleep transistor is an n-channel transistor connected to said common ground terminal.

30. The integrated circuit as claimed in claim 29 wherein said power management circuit applies a voltage from said first power supply terminal to said sleep transistor when not in said power down mode.

31. The integrated circuit as claimed in claim 29 wherein said power management circuit applies a voltage lower than a voltage level of said common ground terminal to said sleep transistor in said power down mode.

32. The integrated circuit as claimed in claim 29 wherein said power management circuit applies a voltage greater than a voltage level of said first power supply terminal to said sleep transistor when not in said power down mode.

33. The integrated circuit as claimed in claim 28 wherein said level shifter retains data in said power down mode.

34. The integrated circuit as claimed in claim 26 wherein said level shifter latches level shifted data.

35. The integrated circuit as claimed in claim 26 wherein said level shifter input transistors are thin gate transistors.

36. The integrated circuit as claimed in claim 26 wherein said level shifter comprises cross-coupled cascode devices and cross-coupled output latching devices.

37. The integrated circuit as claimed in claim 36 wherein said input transistors are thin gate transistors and said cross-coupled output latching devices comprise thick gate transistors.

38. The integrated circuit as claimed in claim 36 further comprising a static random access memory (SRAM) cell built into an output stage of said level shifter.

39. The integrated circuit as claimed in claim 38 further comprising an inverter to prevent inputs of said level shifter from reaching a voltage of said first power supply terminal at the same time.

40. The integrated circuit as claimed in claim 38 wherein said input transistors are configured to withstand voltages higher than that of said first power supply terminal.

41. An integrated circuit comprising:

terminals including a common ground terminal and first and second power supply terminals;

a level shifter configured to latch data shifted from voltage levels defined by said first power supply terminal and said common ground terminal, to voltage levels defined by said second power supply terminal and said common ground terminal, said level shifter having a sleep transistor and input transistors, said sleep transistor in series with an electrical connection to said common ground terminal, and said input transistors driven by inputs at voltage levels defined by said first power supply terminal and said common ground terminal; and

power management circuitry configured to control power consumed by said level shifter using said sleep transistor.

42. The integrated circuit as claimed in claim 41 wherein said second power supply terminal provides a higher voltage than said first power supply terminal.

43. The integrated circuit as claimed in claim 41 wherein said level shifter is built into an input/output pad cell configured to interface with chip core logic.

44. The integrated circuit as claimed in claim 41 wherein said sleep transistor enables a power down mode.

45. The integrated circuit as claimed in claim 44 wherein said sleep transistor is an n-channel transistor connected to said common ground terminal.

46. The integrated circuit as claimed in claim 45 wherein said power management circuit applies a voltage from said first power supply terminal to said sleep transistor when not in said power down mode.

47. The integrated circuit as claimed in claim 45 wherein said power management circuit applies a voltage lower than a voltage level of said common ground terminal to said sleep transistor in said power down mode.

48. The integrated circuit as claimed in claim 45 wherein said power management circuit applies a voltage greater than a voltage level of said first power supply terminal to said sleep transistor when not in said power down mode.

49. The integrated circuit as claimed in claim 44 wherein said level shifter retains data in said power down mode.

50. The integrated circuit as claimed in claim 41 wherein said level shifter input transistors are thin gate transistors.

51. The integrated circuit as claimed in claim 41 wherein said level shifter comprises cross-coupled cascode devices and cross-coupled output latching devices.

52. The integrated circuit as claimed in claim 51 wherein said input transistors are thin gate transistors and said cross-coupled output latching devices comprise thick gate transistors.

53. The integrated circuit as claimed in claim 51 further comprising a static random access memory (SRAM) cell built into an output stage of said level shifter.

54. The integrated circuit as claimed in claim 53 further comprising an inverter to prevent inputs of said level shifter from reaching a voltage of said first power supply terminal at the same time.

55. The integrated circuit as claimed in claim 53 wherein said input transistors are configured to withstand voltages higher than that of said first power supply terminal.

56. A method for operating an integrated circuit, the method comprising:

providing first and second power supply terminals;

translating binary data with a level shifter from voltage levels defined by said first power supply terminal and a common ground terminal to voltage levels defined by said second power supply and said common ground terminal;

driving level shifter input transistors with voltage levels defined by said first power supply terminal and said common ground terminal;

preventing inputs of said level shifter from reaching the voltage level of said first power supply terminal at the same time; and

controlling power consumed by said level shifter with a sleep transistor.

57. The method as claimed in claim 56 wherein said second power supply terminal provides a higher voltage than said first power supply terminal.

58. The method as claimed in claim 56 further comprising latching level shifted data.

59. The method as claimed in claim 56 wherein controlling power consumed by said level shifter includes enabling a power down mode.

60. The method as claimed in claim 59 further comprising applying voltage from said first power supply terminal to said sleep transistor when not in said power down mode.

61. The method as claimed in claim 59 further comprising applying a voltage lower than that of said common ground terminal to said sleep transistor in said power down mode.

62. The method as claimed in claim 59 further comprising applying a voltage greater than the voltage level of said first power supply terminal to said sleep transistor when not in said power down mode.

63. The method as claimed in claim 59 further comprising retaining data with said level shifter in said power down mode.