Circuit configurations having four terminal JFET devices

• US 7,592,841 B2
• Filed: 06/13/2006
• Issued: 09/22/2009
• Est. Priority Date: 05/11/2006
• Status: Expired due to Fees

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: SuVolta, Inc.
• Inventors: Kapoor, Ashok Kumar
• Primary Examiner(s): Le, Don P
• Application Number:
  US11/452,442
• Publication Number:
  US 20070262793A1
• Time in Patent Office: 1,197 Days
• Field of Search: 326/37, 326/38, 326101-104, 326/112, 326/119, 326/121, 326 82- 87
• US Class Current: 326/121
• CPC Class Codes: H01L 2029/7857 of the accumulation type
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/8086 Thin film JFET's
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 19/09403 using junction field-effect transistors H03K19/096 takes precedence

Abstract

Circuits using four terminal junction field effect transistors (JFETs) are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or analog circuit with such four terminal JFETs operating in a linear or nonlinear mode.

Claims

1. A logic circuit, comprising:

at least one input node;

at least one output node; and

at least one junction field effect transistor (JFET) coupled between the at least one input node and output node that includes a first gate and a second gate of a first conductivity type and a channel region of a second conductivity type between the first gate and second gate, the channel region connecting a source region to a drain region both of the second conductivity type;

wherein

one of the front gate or back gate is coupled to receive a tri-state signal that places the at least one JFET into a relatively high impedance state and the other of the front gate or back gate is coupled to receive an input signal.

2. The logic circuit of claim 1, wherein

the JFET is selected from the group consisting of an n-channel device and a p-channel device.

3. The logic circuit of claim 1, wherein:

the logic circuit comprises a plurality of JFETs having first and second gates, including at least one n-channel JFET having a source-drain path coupled between a first internal node and a low power supply node and at least one p-channel JFET having a source-drain path coupled between the first internal node and a high power supply node.

4. The logic circuit of claim 3, wherein:

the at least one p-channel JFET has a front gate coupled to a first input node and a back gate connected to a first predetermined potential, and the at least one n-channel JFET has a front gate coupled to the first input node and a back gate connected to a the first predetermined potential, the first internal node is coupled to the output node, and the logic circuit provides an inverter function.

5. The logic circuit of claim 1, wherein:

the logic circuit comprises at least one JFET of a first conductivity type and at least one JFET of a second conductivity type,

the JFET of the first conductivity type being a single gate depletion mode device that provides a low impedance path in response to a first logic level at either the front gate or back gate of the first conductivity type JFET, and

the JFET of the second conductivity type being a single gate enhancement mode device that provides a low impedance path only in response to a second logic at both the front gate or back gate of the second conductivity type JFET.

6. The logic circuit of claim 1, wherein:

the logic circuit comprises a plurality of JFETs having first and second gates, including a plurality of JFETs of a first channel conductivity type each having a source-drain path coupled between a first power supply node and an internal node, at least one JFET of the first channel conductivity type having a front gate coupled to a first input node and a back gate coupled to a second input node, and a plurality of JFETs of a second channel conductivity type each having a source-drain path arranged in series with one another between the internal node and a second power supply node, at least one JFET of the second channel conductivity type having a front gate coupled to the first input node and a back gate coupled to the second input node.

7. The logic circuit of claim 1, wherein:

the at least one JFET includes

at least one dynamic precharge JFET having a source-drain path coupled to a power supply node and a front gate and back gate commonly connected to a clock signal the periodically varies between logic levels, and

at least one logic determining JFET having a source-drain path coupled in series with the source-drain path of dynamic precharge JFET, a front gate coupled to a first input signal node and a back gate coupled to a second input signal node.

8. The logic circuit of claim 1, wherein:

the at least one JFET includes an input switching JFET having a first end of a source-drain path coupled to a first input node, a front gate coupled to a first signal node and a back gate connected to a second signal node, the first input node and second input nodes varying the threshold voltage of the at least one JFET; and

a driver circuit having an input coupled to a second end of the source-drain path that drives a driver output signal between at least first and second levels based on the threshold voltage of the at least one JFET.

9. The logic circuit of claim 1, wherein:

the at least one JFET includes

a first JFET having a source-drain path coupled between a first input node and a first output node, a front gate coupled to receive a first multiplexer (MUX) control signal, a back gate coupled to receive a second MUX control signal, and

a second JFET having a source-drain path coupled between a second input node and the first output node, a front gate coupled to receive an inverse first MUX control signal, a back gate coupled to receive an inverse second MUX control signal.

10. The logic circuit of claim 1, wherein:

the at least one JFET includes

a first JFET of a first channel conductivity type having a source coupled to a first supply node, a drain coupled to a first latch node and a gate coupled to a first input node,

a second JFET of the first channel conductivity type having a source coupled to the first supply node, a drain coupled to a second latch node and a gate coupled to a second input node,

a first JFET of a second channel conductivity type having a source coupled to a second supply node, a drain coupled to the first latch node and a gate coupled to the first input node, and

a second JFET of the second channel conductivity type having a source coupled to the second supply node, a drain coupled to the second latch node and a gate coupled to the second input node.

11. The logic circuit of claim 1, wherein:

the at least one JFET includes a plurality of JFETs, each such JFET having a back gate coupled to receive an enable signal that increases the conductivity of the channel in a first mode of operation and decreases the conductivity of the channel in a second mode of operation.

12. The logic circuit of claim 1, wherein:

the at least one JFET includes a polysilicon gate of the first conductivity type formed over a semiconductor substrate that includes the channel region, drain region, source region, and second gate.

13. The logic circuit of claim 1, wherein:

the at least one JFET includes a first polysilicon gate of the first conductivity type formed on a first side of the channel region, and a second polysilicon gate of the first conductivity type formed on a second side of the channel region that opposes the first side of the channel region.

14. A circuit that alters the conductivity of a transistor channel by operation of two independently controlled control terminals, comprising:

at least one junction field effect transistor (JFET) having a source-drain path coupled to a signal output node, a first gate of a first conductivity type coupled to receive a first input signal and a second gate of the first conductivity type coupled to receive a second input signal different from the first input signal, a channel region of a second conductivity type disposed between the first gate and second gate, the channel region connecting a source region to a drain region both of the second conductivity type; and

a load circuit coupled between the drain of the at least one JFET and a first power supply node.

15. The circuit of claim 14, wherein:

the first gate is coupled to receive a first periodic signal,

the second gate is coupled to receive a second periodic signal, and

the drain generates an output signal indicating at least one type of phase difference between the first periodic signal and second periodic signal.

16. The circuit of claim 14, further including:

a filter circuit coupled to the drain that filters out at least one frequency range of the output signal.

17. The circuit of claim 14, wherein:

the at least one JFET includes a polysilicon gate of the first conductivity type formed over a semiconductor substrate that includes the channel region, drain region, and source region.

18. An integrated circuit, comprising:

a plurality of junction field effect transistors (JFETs) formed in a semiconductor substrate, each JFET including a first gate and a second gate of a first conductivity type, a channel region between the first gate and second gate of a second conductivity type connecting a source region to a drain region both of the second conductivity type, at least a first JFET having the first gate controlled according to a first signal and the second gate controlled according to a second signal;

the plurality of JFETs including n-channel JFETs in which the first conductivity type is p-type and the second conductivity type is n-type; and

the plurality of JFETs further including p-channel JFETs in which the first conductivity type is n-type and the second conductivity type is p-type.

19. The integrated circuit of claim 18, wherein:

at least one of the JFET is a single gate depletion mode device that provides a low impedance source-drain path in response to either its first gate or second gate being at a first logic level.

20. The integrated circuit of claim 18, wherein:

at least one of the JFETs is a single gate enhancement mode device that provides a low impedance source-drain path in response to both its first gate or second gate being at a first logic level, and not providing the low impedance source-drain path when only one of the first or second gates is at the first logic level.

21. The integrated circuit of claim 18, wherein:

the first JFET is a JFET of the first conductivity type; and

the plurality of JFETs includes at least a second JFET of the second conductivity type, the first gate controlled according to a third signal and the second gate controlled according to a fourth signal.