Configurable delay chain with stacked inverter delay elements

• US 7,592,842 B2
• Filed: 12/18/2007
• Issued: 09/22/2009
• Est. Priority Date: 12/23/2004
• Status: Active Grant

• Current Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Original Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Inventors: Masleid, Robert Paul
• Primary Examiner(s): Chang; Daniel D
• Application Number:
  US12/002,988
• Publication Number:
  US 20080129342A1
• Time in Patent Office: 644 Days
• Field of Search: 326/112, 326/113, 326/119, 326/121, 326/122, 327/149, 327/161, 327/263, 327/276, 327/393, 327/395
• US Class Current: 326/121
• CPC Class Codes: H03K 2005/00039 having four transistors serially
• CPC Class Codes: H03K 5/131 Digitally controlled

Abstract

A stacked inverter delay chain. The stacked inverter delay chain includes a plurality of stacked inverter delay elements. A switch circuit is included and is coupled to the stacked inverter delay elements and configured to select at least one of the plurality of stacked inverter delay elements to create a delay signal path. The delay signal path has an amount of delay in accordance with a number of stacked inverter delay elements comprising the delay signal path. An input is coupled to a first stacked inverter delay element of the delay signal path to receive an input signal and an output is coupled to the switch circuit and is coupled to the delay signal path to receive a delayed version of the input signal after propagating through the delay signal path.

Claims

1. A method of delaying a signal comprising:

selecting at least one of a plurality of stacked inverter delay elements using a switch circuit to create a delay signal path, wherein each stacked inverter delay element includes a greater number of n-type devices than p-type devices;

coupling an input signal to a first stacked inverter delay element of the delay signal path;

propagating the input signal through the delay signal path; and

receiving a resulting output signal from a last stacked inverter delay element of the delay signal path such that the resulting output signal is a delayed version of the input signal.

2. The method of claim 1 wherein each of the plurality of stacked inverter delay elements comprise at least five active devices.

3. The method of claim 1 wherein said first stacked inverter circuit comprises two p-type devices and three n-type devices.

4. The method of claim 1 wherein the switch circuit is configured to adjust an amount of delay for the delay signal path by adjusting a number of the plurality of stacked inverter delay elements in the delay signal path.

5. The method of claim 1 wherein each of the plurality of stacked inverter delay elements is configured to add an incremental amount of delay to the input signal when switched into the delay signal path by the switch circuit.

6. The method of claim 1 wherein the input signal propagates from the first stacked inverter delay element to a subsequent stacked inverter delay element using a substantially direct connection.

7. The method of claim 1 wherein the switch circuit is configured to store a plurality of configuration bits to select a number of stacked inverter delay elements comprising the delay signal path.

8. The method of claim 7 wherein an amount of delay added to the input signal is adjustable in accordance with setting the configuration bits in the switch circuit.

9. A stacked inverter delay chain, comprising:

a plurality of stacked inverter delay elements, each stacked inverter delay element including a greater number of n-type devices than p-type devices;

a switch circuit coupled to the stacked inverter delay elements and configured to select at least one of the plurality of stacked inverter delay elements to create a delay signal path having an amount of delay in accordance with a number of stacked inverter delay elements comprising the delay signal path;

an input coupled to a first stacked inverter delay element of the delay signal path to receive an input signal; and

an output coupled to the switch circuit, wherein the output is coupled to the delay signal path to receive a delayed version of the input signal after propagating through the delay signal path.

10. The stacked inverter delay chain of claim 9, wherein each of the stacked inverter delay elements further comprises:

a first plurality of devices of p-type coupled in series;

a second plurality of devices of n-type coupled in series; and

wherein said first and said second pluralities of devices are coupled in series and comprise at least five active devices.

11. The stacked inverter delay chain of claim 10 wherein said first plurality of devices comprises two p-type devices.

12. The stacked inverter delay chain of claim 11 wherein said second plurality of devices of an opposite type comprises three n-type devices.

13. The stacked inverter delay chain of claim 10 wherein each of the plurality of stacked inverter delay elements are configured for a lower leakage current than an inverter comprising only two active devices.

14. The stacked inverter delay chain of claim 10 wherein a gate of each of the plurality of stacked inverter delay elements is coupled to receive the input signal.

15. The stacked inverter delay chain of claim 10 wherein the switch circuit is configured to adjust an amount of delay for the delay signal path by adjusting a number of the plurality of stacked inverter delay elements in the delay signal path.

16. The stacked inverter delay chain of claim 10 wherein each of the plurality of stacked inverter delay elements is configured to add an incremental amount of delay to the input signal when switched into the delay signal path by the switch circuit.

17. The stacked inverter delay chain of claim 10 wherein the input signal propagates from the first stacked inverter delay element to a subsequent stacked inverter delay element using a substantially direct connection.

18. The stacked inverter delay chain of claim 10 wherein the switch circuit is configured to store a plurality of configuration bits to select a number of stacked inverter delay elements comprising the delay signal path.

19. The stacked inverter delay chain of claim 18 wherein an amount of delay added to the input signal is adjustable in accordance with the setting of the configuration bits in the switch circuit.

20. A stacked inverter delay chain comprising:

a plurality of stacked inverter delay elements, wherein each stacked inverter delay element comprises;

two stacked inverter circuits coupled in series, each of said stacked inverter circuits comprising;

at least two p-type devices coupled in series; and

at least three n-type devices coupled in series, wherein each stacked inverter delay element incorporates a greater number of n-type devices than p-type devices;

a switch circuit coupled to the stacked inverter delay elements and configured to select at least one of the plurality of stacked inverter delay elements to create a delay signal path having an amount of delay in accordance with a number of stacked inverter delay elements comprising the delay signal path;

an input coupled to a first stacked inverter delay element of the delay signal path to receive an input signal; and

an output coupled to the switch circuit, wherein the output is coupled to the delay signal path to receive a delayed version of the input signal after propagating through the delay signal path.

21. The stacked inverter delay chain of claim 20 wherein the two stacked inverter circuits are substantially identical.

22. The stacked inverter delay chain of claim 21 wherein each of the stacked inverter circuits comprises two p-type devices.

23. The stacked inverter delay chain of claim 20 wherein a gate of all devices of each stacked inverter delay element is coupled to the input signal.

24. The stacked inverter delay chain of claim 20 wherein each stacked inverter delay element comprises:

a first p-type device comprising a first terminal coupled to an operating voltage;

a second p-type device comprising a first terminal coupled to a second terminal of said first device;

a third n-type device type comprising a first terminal coupled to a second terminal of said second device;

a fourth n-type device type comprising a first terminal coupled to a second terminal of said third device;

a fifth n-type device comprising a first terminal coupled to a second terminal of said fourth device;

said fifth n-type device further comprising a second terminal coupled to a ground reference of said integrated circuit, wherein third terminals of said first, second, third, fourth and fifth devices are coupled together forming an input to said integrated circuit; and

an output of said integrated circuit coupled to said second terminal of said second p-type device.