High-speed communication system with a feedback synchronization loop

• US 7,593,470 B2
• Filed: 07/16/2008
• Issued: 09/22/2009
• Est. Priority Date: 08/11/1999
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Segaram, Para K.
• Primary Examiner(s): BURD, KEVIN MICHAEL
• Application Number:
  US12/174,128
• Publication Number:
  US 20080273647A1
• Time in Patent Office: 433 Days
• Field of Search: 375/257, 375/354, 375/371, 375/258, 375/219, 375/355, 375/316
• US Class Current: 375/257
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

In a communications device having a physical layer device and a processing device connected to the physical layer device, the number of input/output (I/O) ports required for communication between the devices in the gigabit range is substantially reduced by utilizing millivolt differential I/O drivers and receivers. In addition, a calibration feedback loop synchronizes the data and clock signals on the processing device, thereby eliminating the need to recover the clock on the processing device.

Claims

1. A communication system comprising:

a first processing circuit having a first transmitter to transmit a first clock signal, at least one second transmitter to transmit either a second clock signal or a respective data signal, a first switch circuit to select either the second clock signal or the respective data signal to be transmitted by the at least one second transmitter, and a comparator; and

a second processing circuit having a first receiver to receive the first clock signal from the first transmitter, at least one second receiver to receive either the second clock signal or the respective data signal from the at least one second transmitter, a third transmitter to transmit the first clock signal or the second clock signal, and a second switch circuit to select the first clock signal or the second clock signal to be transmitted by the third transmitter;

wherein the comparator compares a phase of the first clock signal received from the third transmitter at a first time with a phase of the second clock signal received from the third transmitter at a second time.

2. The communication system of claim 1, wherein the third transmitter is further configured to transmit the respective data signal, and the second switch circuit is further configured to select the respective data signal to be transmitted by the third transmitter.

3. The communication system of claim 2, wherein the comparator is further configured to compare a phase of the first clock signal received from the third transmitter at the first time with a phase of the respective data signal received from the third transmitter at a third time.

4. The communication system of claim 1, wherein the first processing circuit further comprises a recovery circuit to generate a recovered clock signal based at least in part upon the comparison of the phase of the first clock signal received from the third transmitter at the first time with the phase of the second clock signal received from the third transmitter at the second time.

5. A communication system comprising:

a first processing circuit having a first transmitter to transmit a first clock signal, a plurality of second transmitters each to transmit either a second clock signal or a respective one of a plurality of data signals, a first switch circuit to select either the second clock signal or a respective one of the plurality of data signals to be transmitted by each of the plurality second transmitters, and a comparator; and

a second processing circuit having a first receiver to receive the first clock signal from the first transmitter, a plurality of second receivers each to receive either the second clock signal or a respective one of the plurality of data signals from a respective one of the plurality of second transmitters, a plurality of third transmitters to transmit the first clock signal or the second clock signal, and a second switch circuit to select the first clock signal or the second clock signal to be transmitted by the plurality of third transmitters;

wherein the comparator compares a phase of the first clock signal received from at least one of the plurality of third transmitters at a first time with a phase of the second clock signal received from the at least one of the plurality of third transmitters at a second time.

6. The communication system of claim 5, wherein each of the plurality of third transmitters is further configured to transmit a respective one of the plurality of data signals, and the second switch circuit is further configured to select respective ones of the plurality of data signals to be transmitted by the plurality of third transmitters.

7. The communication system of claim 6, wherein the comparator is further configured to compare a phase of the first clock signal received from at least one of the plurality of third transmitters at the first time with a phase of a respective one of the plurality of data signals received from the at least one of the plurality of third transmitters at a third time.

8. The communication system of claim 5, wherein the first processing circuit further comprises a recovery circuit to generate a recovered clock signal based at least in part upon the comparison of the phase of the first clock signal received from at least one of the plurality of third transmitters at the first time with the phase of the second clock signal received from the at least one of the plurality of third transmitters at the second time.

9. A communication system comprising:

a first processing circuit having a first transmitter to transmit a first clock signal, a second transmitter to transmit a second clock signal, a first receiver, and a comparator; and

a second processing circuit having a second receiver to receive the first clock signal from the first transmitter, a third receiver to receive the second clock signal from the second transmitter, a third transmitter to transmit the first clock signal or the second clock signal to the first receiver, and a switch circuit to select the first clock signal or the second clock signal to be transmitted to the first receiver by the third transmitter;

wherein the comparator compares a phase of the first clock signal received from the third transmitter at a first time with a phase of the second clock signal received from the third transmitter at a second time.

10. The communication system of claim 9, wherein the second transmitter is further configured to transmit a data signal, the third transmitter is further configured to transmit the data signal, and the second switch circuit is further configured to select the data signal to be transmitted by the third transmitter.

11. The communication system of claim 10, wherein the comparator is further configured to compare a phase of the first clock signal received from the third transmitter at the first time with a phase of the data signal received from the third transmitter at a third time.

12. The communication system of claim 9, wherein the first processing circuit further comprises a recovery circuit to generate a recovered clock signal based at least in part upon the comparison of the phase of the first clock signal received from the third transmitter at the first time with the phase of the second clock signal received from the third transmitter at the second time.

13. A communication system comprising:

a transmission medium;

a first processing circuit having a first receiver to receive a first serial data signal from the transmission medium, a clock generator to generate a first clock signal and a second clock signal, a first transmitter to transmit the first clock signal, a second transmitter to transmit either the second clock signal or the first serial data signal, a first switch circuit to select either the second clock signal or the first serial data signal to be transmitted by the second transmitter, and a comparator; and

a second processing circuit having a second receiver to receive the first clock signal from the first transmitter, a third receiver to receive either the second clock signal or the first serial data signal from the second transmitter, a third transmitter to transmit the first clock signal or the second clock signal, and a second switch circuit to select the first clock signal or the second clock signal to be transmitted by the third transmitter;

wherein the comparator compares a phase of the first clock signal received from the third transmitter at a first time with a phase of the second clock signal received from the third transmitter at a second time.

14. The communication system of claim 13, wherein the first processing circuit further comprises a fourth transmitter to transmit a second serial data signal to the transmission medium.

15. The communication system of claim 13, wherein the third transmitter is further configured to transmit the first serial data signal, and the second switch circuit is further configured to select the first serial data signal to be transmitted by the third transmitter.

16. The communication system of claim 15, wherein the comparator is further configured to compare a phase of the first clock signal received from the third transmitter at the first time with a phase of the first serial data signal received from the third transmitter at a third time.

17. The communication system of claim 13, wherein the first processing circuit further comprises a recovery circuit to generate a recovered clock signal based at least in part upon the comparison of the phase of the first clock signal received from the third transmitter at the first time with the phase of the second clock signal received from the third transmitter at the second time.

18. A processing circuit comprising:

a plurality of first receivers to receive a respective plurality of first serial data signals from a transmission medium;

a clock generator to generate a first clock signal and a second clock signal;

a first transmitter to transmit the first clock signal;

a plurality of second transmitters each to transmit either the second clock signal or a respective one of the plurality of first serial data signals;

a switching circuit to select either the second clock signal or one of the plurality of first serial data signals to be transmitted by a respective one of the plurality of second transmitters;

a plurality of second receivers to receive the first clock signal and the second clock signal; and

a comparator to compare a phase of the first clock signal received by at least one of the plurality of second receivers at a first time with a phase of the second clock signal received by the at least one of the plurality second receivers at a second time.

19. The processing circuit of claim 18, further comprising:

a plurality of first transmitters to transmit a respective plurality of second serial data signals to the transmission medium.

20. The processing circuit of claim 18, wherein each of the plurality of second receivers is further configured to receive a respective one of the plurality of first serial data signals.

21. The processing circuit of claim 19, wherein the comparator is further configured to compare a phase of the first clock signal received by at least one of the plurality of second receivers at the first time with a phase of a respective one of the plurality of first serial data signal received by the at least one of the plurality of second receivers at a third time.

22. The processing circuit of claim 18, further comprising a recovery circuit to generate a recovered clock signal based at least in part upon the comparison of the phase of the first clock signal received by at least one of the plurality of second receivers at the first time with a phase of the second clock signal received by the at least one of the plurality second receivers at the second time.