Receiver assembly and method for multi-gigabit wireless systems

• US 7,593,704 B2
• Filed: 03/31/2006
• Issued: 09/22/2009
• Est. Priority Date: 03/31/2005
• Status: Active Grant

• Current Assignee: Georgia Tech Research Corporation (University System of Georgia)
• Original Assignee: Georgia Tech Research Corporation (University System of Georgia)
• Inventors: Pinel, Stephane, Laskar, Joy
• Primary Examiner(s): NGUYEN, SIMON
• Application Number:
  US11/394,497
• Publication Number:
  US 20060232469A1
• Time in Patent Office: 1,271 Days
• Field of Search: 455/63.4, 455/502, 455132-136, 455/208, 455/214, 455/265, 455/272, 455/562.1, 455/313, 375/145, 375324-328, 375/343, 375/347, 375/349, 375/354, 375/355, 375147-150
• US Class Current: 455/130
• CPC Class Codes: H04B 7/0808 comparing all antennas before reception
• CPC Class Codes: H04B 7/088 using beam selection

Abstract

The present invention describes a receiver assembly for receiving an analog signal and converting the analog signal to a digital signal. The receiver assembly is, preferably, capable of receiving a signal operating at approximately 60 GHz. The receiver assembly includes a filter, a down converter, a demodulator, a latch, a FIFO, and a logic circuit. A method of converting the 60 GHz analog signal to a digital signal is also described.

Claims

1. A method of converting an analog signal to a digital signal, wherein the analog signal has a frequency of approximately 60 GHz, the method comprising:

receiving at least two analog signals operating at approximately 60 GHz with a plurality of antennas;

processing the at least two analog signals in parallel;

feeding a first analog signal received from the plurality of antennas to a first amplifier;

feeding a second analog signal received from the plurality of antennas to a second amplifier;

amplifying the first and second analog signals to create a first cleaned signal and a second cleaned signal;

converting the frequency of the first and second cleaned signals by down converting the first and second cleaned signals;

demodulating a first down converted signal for clock signal and data signal recovery;

demodulating a second down converted signal for clock signal and data signal recovery;

synchronizing in parallel the demodulated signals;

correlating the demodulated signals to known sequences for alignment; and

outputting a combined digital signal.

2. The method of claim 1, wherein the combined digital signal is subjected to error detection and error correction prior to output.

3. A receiver assembly comprising:

an N-array antenna assembly comprising a plurality of antennas, wherein the plurality of antennas are adapted to receive an analog signal at a frequency of approximately 60 GHz;

a first amplifier adapted to receive a first analog signal from a first antenna of the plurality of antennas, amplify the first analog signal, and output a first amplified signal;

a second amplifier adapted to receive a second analog signal from a second antenna of the plurality of antennas, amplify the second analog signal, and output a second amplified signal;

a first down converter for performing a frequency conversion on the first amplified signal and outputting a first down converted signal;

a second down converter for performing a frequency conversion on the second amplified signal and outputting a second down converted signal;

a first demodulator adapted to recover and output a first data signal and a first clock signal from the first down converted signal;

a second demodulator adapted to recover and output a second data signal and a second clock signal from the second down converted signal;

a latch adapted to synchronize in parallel the first and second data signals and the first and second clock signals;

a FIFO adapted to align the first data signal and the second data signal; and

a logic circuit adapted to correlate the first and second data signals to each other, combine the first data signal and the second data signal from the FIFO, detect and correct errors, and output a digital signal.

4. The receiver assembly of claim 3, the logic circuit emitting a digital signal, and the receiver assembly receiving an analog signal and converting the analog signal to the digital signal.

5. The receiver assembly of claim 3, the plurality of amplifiers comprising low noise amplifiers.

6. The receiver assembly of claim 3, the first and second demodulators comprising a clock and data recovery system for generating a clock signal to the receiver assembly.

7. The receiver assembly of claim 3, each antenna of the plurality of antennas providing approximately 10 dBi of gain, an azimuth 3 dB beam-width of approximately 60 degrees, and an elevation 3 dB beam-width in a range of approximately 30 to 35 degrees.

8. The receiver assembly of claim 3, each antenna of the plurality of antennas including a different orientation.

9. The receiver assembly of claim 3, the N-array antenna assembly providing a sectored coverage of approximately 60 degrees in an azimuth plane.

10. The receiver assembly of claim 8, the N-array antenna assembly providing a sectored coverage of approximately 180 degrees in an elevation plane.

11. A receiver assembly comprising:

a first antenna of an N-array antenna assembly adapted to receive a first portion of an analog signal at a frequency of approximately 60 GHz and provide a first signal;

a second antenna of the N-array antenna assembly adapted to receive a second portion of the analog signal at a frequency of approximately 60 GHz and provide a second signal;

a first amplifier adapted to receive the first signal, amplify the first signal, and output a first amplified signal;

a second amplifier adapted to receive the second signal, amplify the second signal, and output a second amplified signal;

a first down converter adapted to receive the first amplified signal, perform a frequency conversion on the first amplified signal, and output a first down converted signal;

a second down converter adapted to receive the second amplified signal, perform a frequency conversion on the second amplified signal, and output a second down converted signal;

a first demodulator adapted to recover and output a first data signal and a first clock signal from the first down converted signal;

a second demodulator adapted to recover and output a second data signal and a second clock signal from the second down converted signal;

a latch for receiving the first data signal and first clock signal from the first demodulator, the second data signal and second clock signal from the second demodulator, and adapted to synchronize in parallel the demodulated signals;

a FIFO for aligning the first data signal and the second data signal; and

a logic circuit adapted to combine the first data signal and the second data signal from the FIFO and output a combined digital signal.

12. The receiver assembly of claim 11, wherein the FIFO aligns the first data signal and the second data signal in parallel.

13. The receiver assembly of claim 11, the logic circuit using a signal to noise ratio to generate the desired output.

14. The receiver assembly of claim 11, the first antenna having the highest signal-to-noise ratio and the second antenna having the second highest signal-to-noise ratio of the antennas in the N-array antenna assembly.

15. The receiver assembly of claim 11, the logic circuit further adapted to detect and correct errors in the combined digital signal prior to outputting the combined digital signal.