System and method for an asynchronous data buffer having buffer write and read pointers
First Claim
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1. A method, comprising:
- storing read data in sequentially selected data locations of a buffer responsive to a first clock signal;
retrieving read data from sequentially selected data locations of the buffer responsive to a second clock signal;
identifying a first data location in the buffer where read data is stored responsive to the first clock signal;
identifying a second data location in the buffer where read data is retrieved responsive to the second clock signal;
comparing the first data location and the second data location to determine a number of data locations between the first data location and the second data location, the number of data locations indicative of a timing offset; and
adjusting timing parameters responsive to the timing offset.
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Abstract
A system and method for facilitating the adjustment of timing parameters between a memory controller operating in a first clock domain and a memory device operating in a second clock domain. A write pointer and a read pointer are monitored to provide a write-read pointer offset representing the timing between when read data is made available by the memory device and when the read data is retrieved by the memory controller. Based on the write-read pointer offset, adjustment to different timing parameters can be made.
294 Citations
77 Claims
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1. A method, comprising:
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storing read data in sequentially selected data locations of a buffer responsive to a first clock signal; retrieving read data from sequentially selected data locations of the buffer responsive to a second clock signal; identifying a first data location in the buffer where read data is stored responsive to the first clock signal; identifying a second data location in the buffer where read data is retrieved responsive to the second clock signal; comparing the first data location and the second data location to determine a number of data locations between the first data location and the second data location, the number of data locations indicative of a timing offset; and adjusting timing parameters responsive to the timing offset. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method, comprising:
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identifying a first data location in a buffer where read data is stored in responsive to the first clock signal, the read data stored in sequentially selected data locations of the buffer; identifying a second data location in the buffer where read data is retrieved from responsive to the second clock signal, the read data retrieved from sequentially selected data locations of the buffer; comparing the first data location and the second data location to determine a number of data locations between the first data location and the second data location, the number of data locations indicative of a timing offset; and executing data transfer operations responsive to the timing offset. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. An apparatus, comprising:
a synchronization module operable to couple data between a first time domain and a second time domain, the synchronization module comprising; a first pointer circuit, the first pointer circuit operable to generate a first pointer signal indicative of a data location in a buffer where data is to be stored in responsive to a first clock signal; a buffer coupled to the first pointer circuit, the buffer having a plurality of data locations; a second pointer circuit, the second pointer circuit operable to generate a second pointer signal indicative of a data location in the buffer where data is to be retrieved from responsive to a second clock signal; a selection circuit coupled to the buffer and the second pointer circuit, the selection circuit operable to selectively couple data stored in the plurality of data locations of the buffer to an output terminal of the selection circuit responsive to the second clock signal; data latch coupled to the output terminal of the selection circuit to latch the data selectively coupled thereto responsive to the first clock signal; and a comparison circuit coupled to the first pointer circuit and the second pointer circuit, the comparison circuit operable to compare the first pointer signal and the second pointer signal to generate a pointer offset signal indicative of a pointer offset. - View Dependent Claims (23, 24, 25, 26, 27, 28)
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29. A memory hub, comprising:
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a link interface adapted to receive memory requests for access to memory locations in at least one memory device of a plurality of memory devices; a memory device interface adapted to receive read data in response to memory requests; a memory controller coupled to the link interface and the memory device interface, the memory controller operable to couple memory requests to the memory device interface responsive to memory requests received from the link interface and further operable to adjust timing parameters responsive to a pointer offset signal indicative of a pointer offset; and a synchronization module coupled to a memory device, the memory device interface and the memory controller, the memory device operating according to a first clock signal, the synchronization module operable to couple read data from the memory device to the memory controller, the memory controller operable to receive memory requests from the link interface responsive to a second clock signal, the synchronization module comprising; a first pointer circuit, the first pointer circuit operable to generate a first pointer signal indicative of a data location in a buffer where data is to be stored in responsive to the first clock signal; a second pointer circuit, the second pointer circuit operable to generate a second pointer signal indicative of a data location in the buffer where data is to be retrieved from responsive to the second clock signal; and a comparison circuit coupled to the first pointer circuit and the second pointer circuit, the comparison circuit operable to compare the first pointer signal and the second pointer signal to generate the pointer offset signal. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44)
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45. A memory module, comprising:
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a plurality of memory devices; a memory bus coupled to the plurality of memory devices; and a memory hub coupled to the plurality of memory devices through the memory bus, the memory hub comprising; a link interface adapted to receive memory requests for access to memory locations in at least one memory device of the plurality of memory devices; a memory device interface adapted to receive read data in response to memory requests; a memory controller coupled to the link interface and the memory device interface, the memory controller operable to couple memory requests to the memory device interface responsive to memory requests received from the link interface and further operable to adjust timing parameters responsive to a pointer offset signal indicative of a pointer offset; and a synchronization module coupled to a memory device, the memory device interface and the memory controller, the memory device operating according to a first clock signal, the synchronization module operable to couple read data from the memory device to the memory controller, the memory controller operable to receive memory requests from the link interface responsive to a second clock signal, the synchronization module comprising; a first pointer circuit, the first pointer circuit operable to generate a first pointer signal indicative of a data location in a buffer where data is to be stored in responsive to the first clock signal; a second pointer circuit, the second pointer circuit operable to generate a second pointer signal indicative of a data location in the buffer where data is to be retrieved from responsive to the second clock signal; and a comparison circuit coupled to the first pointer circuit and the second pointer circuit, the comparison circuit operable to compare the first pointer signal and the second pointer signal to generate the pointer offset signal. - View Dependent Claims (46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60)
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61. A processor-based system, comprising:
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a processor; a system controller coupled to the processor; a memory bus coupled to the system controller, the memory bus adapted to transmit memory requests and responses; and a plurality of memory modules, each of the plurality of memory modules comprising; a plurality of memory devices; a memory bus coupled to the plurality of memory devices; and a memory hub coupled to the plurality of memory devices through the memory bus, the memory hub comprising; a link interface adapted to receive memory requests for access to memory locations in at least one memory device of a plurality of memory devices; a memory device interface adapted to receive read data in response to memory requests; a memory controller coupled to the link interface and the memory device interface, the memory controller operable to couple memory requests to the memory device interface responsive to memory requests received from the link interface and further operable to adjust timing parameters responsive to a pointer offset signal indicative of a pointer offset; and a synchronization module coupled to a memory device, the memory device interface and the memory controller, the memory device operating according to a first clock signal, the synchronization module operable to couple read data from the memory device to the memory controller, the memory controller operable to receive memory requests from the link interface responsive to a second clock signal, the synchronization module comprising; a first pointer circuit, the first pointer circuit operable to generate a first pointer signal indicative of a data location in a buffer where data is to be stored in responsive to the first clock signal; a second pointer circuit, the second pointer circuit operable to generate a second pointer signal indicative of a data location in the buffer where data is to be retrieved from responsive to the second clock signal; and a comparison circuit coupled to the first pointer circuit and the second pointer circuit, the comparison circuit operable to compare the first pointer signal and the second pointer signal to generate the pointer offset signal. - View Dependent Claims (62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77)
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Specification