Apparatus and method for testing semiconductor memory device

• US 7,594,148 B2
• Filed: 12/27/2004
• Issued: 09/22/2009
• Est. Priority Date: 07/29/2004
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Do, Chang-Ho
• Primary Examiner(s): Britt; Cynthia
• Application Number:
  US11/024,376
• Publication Number:
  US 20060041804A1
• Time in Patent Office: 1,730 Days
• Field of Search: 365/200, 365/201, 714/42, 714/54, 714/718
• US Class Current: 714/718
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 2029/1204 Bit line control
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 29/12005 comprising voltage or current generators

Abstract

A semiconductor memory device for performing a reliability test includes a write driving block for generating a predetermined test voltage in a test mode and delivering a data inputted from an external circuit into the local I/O line pair during a data access operation in a normal mode, a local I/O line pair coupled to the write driving block for receiving the predetermined test voltage in the test mode, and a cell array having a plurality of unit cells and a plurality of bit line pairs respectively having first and second bit lines and coupled to at least one unit cell for receiving the predetermined test voltage from each local I/O line pair to thereby check a result of the reliability test in the test mode.

Claims

1. A semiconductor memory device for performing a reliability test, comprising:

a write driving block for generating a predetermined test voltage in response to a plurality of test control signals during a test mode and delivering a data inputted from an external circuit into the local I/O line pair during a data access operation during a normal mode;

a local I/O line pair coupled to the write driving block for receiving the predetermined test voltage from the write driving block during the test mode;

a cell array having a plurality of unit cells and a plurality of bit line pairs respectively having first and second bit lines and coupled to at least one unit cell for receiving the predetermined test voltage from each local I/O line pair to thereby check a result of the reliability test during the test mode; and

a test decision block enabled by a test mode enable signal for outputting the plurality of test control signals to the write driving block.

2. The semiconductor memory device as recited in claim 1, further comprising:

a plurality of segment I/O line pairs, each having first and second segment I/O lines and each coupled between each bit line pair and each local I/O line pair;

a plurality of first switching block for connecting or disconnecting each bit line pair to each segment I/O line pair in response to a first control signal; and

a plurality of second switching block for connecting or disconnecting each segment I/O line pair to each local I/O line pair in response to a second control signal,

wherein the first and second control signals are respectively corresponded to an address and a command signal inputted to the semiconductor memory device.

3. The semiconductor memory device as recited in claim 2, wherein the write driving block includes:

a data receiving block for receiving the inputted data signal, a precharge command signal and a write enable signal and generating first and second output signals;

a latching block for receiving and latching the first and second output signals respectively to output an inverse first output signal and an inverse second output signal; and

a test voltage generating block for receiving the inverse first output signal, the inverse second output signal and first and second test mode signals to thereby output one of the inputted data signal and the predetermined test voltage to each local I/O line pair in response to the first and second test mode signals.

4. The semiconductor memory device as recited in claim 3, wherein the data receiving block includes:

a first MOS transistor controlled by the precharge command signal for outputting a core voltage as the first output signal;

a second MOS transistor controlled by the inputted data signal through a global I/O line for transmitting a ground;

a third MOS transistor controlled by the write enable signal for outputting the ground transmitted from the second MOS transistor as the first output signal;

a fourth MOS transistor controlled by the precharge command signal for outputting a core voltage as the second output signal;

a first inverter for inverting the inputted data signal;

a fifth MOS transistor controlled by an inverse inputted data signal through a global I/O line for transmitting a ground; and

a sixth MOS transistor controlled by the write enable signal for outputting the ground transmitted from the second MOS transistor as the second output signal.

5. The semiconductor memory device as recited in claim 4, wherein the latching block includes:

a first latching unit constituted with two circularly connected inverters for latching the first output signal and outputting an inverse first output signal to the test voltage generating block; and

a second latching unit constituted with two circularly connected inverters for latching the second output signal and outputting an inverse second output signal to the test voltage generating block.

6. The semiconductor memory device as recited in claim 5, wherein the test voltage generating block includes:

a first NOR gate for receiving the first test mode signal and the inverse second output signal and generating a first pull-up signal according to a result of a logic NOR operation about the first test mode signal and the inverse second output signal;

a second NOR gate for receiving the second test mode signal and the inverse first output signal and outputting a first resultant signal of a logic NOR operation about the first test mode signal and the inverse second output signal;

a third inverter for inverting the first resultant signal to thereby generate as a first pull-down signal;

a third NOR gate for receiving the first test mode signal and the inverse first output signal and generating a second pull-up signal according to a result of a logic NOR operation about the first test mode signal and the inverse first output signal;

a fourth NOR gate for receiving the second test mode signal and the inverse second output signal and outputting a second resultant signal of a logic NOR operation about the first test mode signal and the inverse second output signal;

a third inverter for inverting the second resultant signal to thereby generate as a second pull-down signal;

a seventh MOS transistor controlled by the first pull-up signal for supplying the second local I/O line with a core voltage as one of the inputted data signal and the predetermined test voltage;

a eighth MOS transistor controlled by the first pull-down signal for supplying the first local I/O line with a ground as one of the inputted data signal and the predetermined test voltage;

a ninth MOS transistor controlled by the second pull-up signal for supplying the second local I/O line with a core voltage as one of the inputted data signal and the predetermined test voltage; and

a tenth MOS transistor controlled by the second pull-down signal for supplying the second local I/O line with a ground as one of the inputted data signal and the predetermined test voltage.

7. The semiconductor memory device as recited in claim 6, wherein the write enable signal is activated in response to a write command signal and a test command signal which are inputted from the outside of the semiconductor memory device.

8. The semiconductor memory device as recited in claim 1, further comprising a local I/O line precharge block for precharging the local I/O line pair.

9. The semiconductor memory device as recited in claim 8, wherein the write driving block includes:

a data receiving block for receiving the inputted data signal, a precharge command signal and a write enable signal and generating first and second output signals;

a latching block for receiving and latching the first and second output signals respectively to output an inverse first output signal and an inverse second output signal; and

a test voltage generating block for receiving the inverse first output signal, the inverse second output signal, a first test mode signal, a second test mode signal, a third test mode signal and a fourth test mode signal to thereby output one of the inputted data signal and the predetermined test voltage to each local I/O line pair in response to the first to fourth test mode signals.

10. The semiconductor memory device as recited in claim 9, wherein the data receiving block includes:

a first MOS transistor controlled by a precharge command signal for outputting a core voltage as the first output signal;

a second MOS transistor controlled by the inputted data signal through a global I/O line for transmitting a ground;

a third MOS transistor controlled by a write enable signal for outputting the ground transmitted from the second MOS transistor as the first output signal;

a fourth MOS transistor controlled by the precharge command signal for outputting a core voltage as the second output signal;

a first inverter for inverting the inputted data signal;

a fifth MOS transistor controlled by an inverse inputted data signal through a global I/O line for transmitting a ground; and

a sixth MOS transistor controlled by the write enable signal for outputting the ground transmitted from the second MOS transistor as the second output signal.

11. The semiconductor memory device as recited in claim 10, wherein the latching block includes:

a first latching unit constituted with two circularly connected inverters for latching the first output signal and outputting an inverse first output signal to the test voltage generating block; and

a second latching unit constituted with two circularly connected inverters for latching the second output signal and outputting an inverse second output signal to the test voltage generating block.

12. The semiconductor memory device as recited in claim 10, wherein the test voltage generating block includes:

a first NOR gate for receiving the first test mode signal and the inverse second output signal and generating a first pull-up signal according to a result of a logic NOR operation about the first test mode signal and the inverse second output signal;

a second NOR gate for receiving the second test mode signal and the inverse first output signal and outputting a first resultant signal of a logic NOR operation about the second test mode signal and the inverse second output signal;

a third inverter for inverting the first resultant signal to thereby generate as a first pull-down signal;

a third NOR gate for receiving the third test mode signal and the inverse first output signal and generating a second pull-up signal according to a result of a logic NOR operation about the third test mode signal and the inverse first output signal;

a fourth NOR gate for receiving the fourth test mode signal and the inverse second output signal and outputting a second resultant signal of a logic NOR operation about the fourth test mode signal and the inverse second output signal;

a third inverter for inverting the second resultant signal to thereby generate as a second pull-down signal;

a seventh MOS transistor controlled by the first pull-up signal for supplying the first local I/O line with a core voltage as one of the inputted data signal and the predetermined test voltage;

a eighth MOS transistor controlled by the first pull-down signal for supplying the first local I/O line with a ground as one of the inputted data signal and the predetermined test voltage;

a ninth MOS transistor controlled by the second pull-up signal for supplying the second local I/O line with a core voltage as one of the inputted data signal and the predetermined test voltage; and

a tenth MOS transistor controlled by the second pull-down signal for supplying the second local I/O line with a ground as one of the inputted data signal and the predetermined test voltage.

13. The semiconductor memory device as recited in claim 12, wherein the write enable signal is activated in response to a write command signal and a test command signal which are inputted from the outside of the semiconductor memory device.

14. The semiconductor memory device as recited in claim 1, wherein the predetermined test voltage is applied to one of a basis of even and odd number bit line pairs, a basis of a first and a second bit lines of each bit line pair and a basis of even and odd number bit line pairs and a first and a second bit lines of each bit line pairs.

15. The semiconductor memory device as recited in claim 14, wherein the write driver includes:

an even number write driver coupled to the even number bit line pair; and

an odd number write driver coupled to the odd number bit line pair.

16. A semiconductor memory device for performing a reliability test, comprising:

a test voltage generating block for generating a predetermined test voltage in response to a plurality of test control signals during a test mode;

a local I/O line pair coupled to the test voltage generating block for receiving the predetermined test voltage from the test voltage generating block during the test mode;

a cell array having a plurality of unit cells and a plurality of bit line pairs respectively having first and second bit lines and coupled to at least one unit cell for receiving the predetermined test voltage from each local I/O line pair to thereby check a result of the reliability test during the test mode; and

a test decision block enabled by a test mode enable signal for outputting the plurality of test control signals to the write driving block.

17. The semiconductor memory device as recited in claim 16, further comprising:

a local I/O line precharge block for precharging the local I/O line pair; and

a write driver for delivering a data inputted from an external circuit into the local I/O line pair during a data access operation.

18. The semiconductor memory device as recited in claim 16, wherein the predetermined test voltage is applied to one of a basis of even and odd number bit line pairs, a basis of a first and a second bit lines of each bit line pair and a basis of even and odd number bit line pairs and a first and a second bit lines of each bit line pairs.

19. The semiconductor memory device as recited in claim 18, wherein the test voltage generating block includes:

an inverter for inverting a first test voltage control signal;

a first control transistor for outputting a logic high level voltage to a first local I/O line of the local I/O line pair in response to an output signal of the inverter;

a second control transistor for outputting a logic low level voltage to the first local I/O line of the local I/O line pair in response to a second test voltage control signal;

a third control transistor for outputting a logic high level voltage to a second local I/O line of the local I/O line pair in response to an output signal of the inverter; and

a fourth control transistor for outputting a Logic low level voltage to the second local I/O line of the local I/O line pair in response to the second test voltage control signal.

20. The semiconductor memory device as recited in claim 18, wherein the test voltage generating block includes:

a first inverter for inverting a first test voltage control signal;

a first control transistor for outputting a logic high level voltage to a first local I/O line of the local I/O line pair in response to an output signal of the first inverter;

a second control transistor for outputting a logic low level voltage to the first local I/O line of the local I/O line pair in response to a second test voltage control signal;

a second inverter for inverting a third test voltage control signal;

a third control transistor for outputting a logic high level voltage to a second local I/O line of the local I/O line pair in response to an output signal of the second inverter; and

a fourth control transistor for outputting a logic low level voltage to the second local I/O line of the local I/O line pair in response to a fourth test voltage control signal.

21. The semiconductor memory device as recited in claim 18, wherein the test voltage generating block includes:

an even number test voltage generating block coupled to the even number bit line pair; and

an odd number test voltage generating block coupled to the odd number bit line pair.

22. A semiconductor memory device for performing a reliability test, comprising:

a local I/O line precharging block for receiving a plurality of test mode signals, generating a predetermined test voltage for performing a background test in response to the plurality of test mode signals during a test mode and generating a core voltage as a local I/O line precharge voltage during a normal mode;

a local I/O line pair coupled to a test voltage generating block for receiving the predetermined test voltage from the test voltage generating block during the test mode;

a cell array having a plurality of unit cells and a plurality of bit line pairs respectively having first and second bit lines and coupled to at least one unit cell for receiving the predetermined test voltage from each local I/O line pair to thereby check a result of the reliability test in the test mode; and

a test decision block enabled by a test mode enable signal for outputting a plurality of test control signals to a write driver.

23. The semiconductor memory device as recited in claim 22, wherein the write driver delivers a data inputted from an external circuit into the local I/O line pair during a data access operation in a normal mode.

24. The semiconductor memory device as recited in claim 22, wherein predetermined test voltage is applied to one of a basis of even and odd number bit line pairs.

25. The semiconductor memory device as recited in claim 24, wherein the local I/O line precharging block includes:

a precharging block for precharging the local I/O line pair as the core voltage during the normal mode and outputting a logic high level voltage to the local I/O line pair in response to a first test control signal during the test mode;

a ground supplying block for outputting a logic low level voltage to the local I/O line pair in response to a second test control signal during the test mode; and

a control block for receiving a precharge command signal and the first test control signal to thereby control the precharging block during the normal mode and the test mode.

26. The semiconductor memory device as recited in claim 25, wherein the control block includes:

an inverter for converting the first test control signal; and

a logic NOR gate for receiving an output signal of the inverter and the precharge command signal to generate a result signal of the logic NOR operation between the output signal of the inverter and the precharge command signal.

27. The semiconductor memory device as recited in claim 26, wherein the precharging block and the ground supplying block are respectively constituted with three MOS transistors.