×

Fault detecting method and layout method for semiconductor integrated circuit

  • US 7,594,206 B2
  • Filed: 04/24/2006
  • Issued: 09/22/2009
  • Est. Priority Date: 10/29/1999
  • Status: Expired due to Fees
First Claim
Patent Images

1. A computer-implemented layout method for a semiconductor integrated circuit, comprising:

  • omitting from a fault list faults that are difficult to detect; and

    performing by a computer mask layout and wiring of a semiconductor integrated circuit based on a remaining part of the fault list.

View all claims
  • 0 Assignments
Timeline View
Assignment View
    ×
    ×