Fault detecting method and layout method for semiconductor integrated circuit

• US 7,594,206 B2
• Filed: 04/24/2006
• Issued: 09/22/2009
• Est. Priority Date: 10/29/1999
• Status: Expired due to Fees

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Yoshida, Takaki, Shimoda, Reisuke
• Primary Examiner(s): Kik; Phallaka
• Application Number:
  US11/409,033
• Publication Number:
  US 20060236184A1
• Time in Patent Office: 1,247 Days
• Field of Search: 716/4, 716/2, 716/8, 716/12, 716/21, 703/14, 714/25, 714/33, 714/37, 714/741, 702/59, 324/527, 324/537
• US Class Current: 716/136
• CPC Class Codes: G01R 31/2846 using hard- or software simulation or using knowledge-based systems, e.g. expert systems, artificial intelligence or interactive algorithms
• CPC Class Codes: G01R 31/31835 Analysis of test coverage or failure detectability
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

The present invention provides a fault detecting method and a layout method for a semiconductor integrated circuit. The fault detecting method performs detection for faults in a semiconductor integrated circuit using a fault list corresponding to information on sites in the semiconductor integrated circuit where a fault is likely to occur or information required to reduce such faults. In addition, the fault detecting method and the layout method perform ordering of faults with their likelihood and weighting of the faults, taking into consideration physical information on a mask pattern within a chip or records of actual use of cells or functional blocks.

Claims

1. A computer-implemented layout method for a semiconductor integrated circuit, comprising:

omitting from a fault list faults that are difficult to detect; and

performing by a computer mask layout and wiring of a semiconductor integrated circuit based on a remaining part of the fault list.

2. The computer-implemented layout method for a semiconductor integrated circuit according to claim 1, wherein the fault list contains data on a likelihood of occurrence of each fault.

3. The computer-implemented layout method for a semiconductor integrated circuit according to claim 2, wherein the mask layout and the wiring are performed for the semiconductor integrated circuit using a fault list ordered such that each fault is listed according to its likelihood of occurrence.

4. The computer-implemented layout method for a semiconductor integrated circuit according to claim 3, wherein the faults are ordered or weighted according to their likelihood of occurrence based on mask information obtained from a layout device for laying out the semiconductor integrated circuit.

5. The computer-implemented layout method for a semiconductor integrated circuit according to claim 3, further comprising:

obtaining mask information from a layout device for laying out the semiconductor integrated circuit,

calculating a density of a mask pattern based on the mask information obtained from the layout device, and

ordering or weighting the faults according to their likelihood of occurrence depending on the density of the mask pattern.

6. The computer-implemented layout method for a semiconductor integrated circuit according to claim 3, wherein the faults are ordered or weighted according to their likelihood of occurrence using a database for reliability based on records of past use of cells or functional blocks of the semiconductor integrated circuit.

7. The computer-implemented layout method for a semiconductor integrated circuit according to claim 2, wherein the faults are weighted according to their likelihood of occurrence to determine a fault coverage for the mask layout and wiring for the semiconductor integrated circuit.

8. The computer-implemented layout method for a semiconductor integrated circuit according to claim 7, wherein the faults are ordered according to their likelihood of occurrence and are weighted in accordance with this ordering.

9. The computer-implemented layout method for a semiconductor integrated circuit according to claim 8, further comprising:

calculating a fault coverage that is obtained when detecting each fault,

deleting from the fault list in an order of unlikelihood of occurrence faults that are not required to achieve a specified fault coverage, and

performing a fault detecting process for the remaining faults.

10. The computer-implemented layout method for a semiconductor integrated circuit according to claim 8, further comprising:

calculating the fault coverage while carrying out a process for each fault detection in accordance with the ordering, and

stopping the process once a specified fault coverage has been reached.