Gate pullback at ends of high-voltage vertical transistor structure

• US 7,595,523 B2
• Filed: 02/16/2007
• Issued: 09/29/2009
• Est. Priority Date: 02/16/2007
• Status: Expired due to Fees

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Parthasarathy, Vijay, Manley, Martin H.
• Primary Examiner(s): Vu; David
• Application Number:
  US11/707,820
• Publication Number:
  US 20080197418A1
• Time in Patent Office: 956 Days
• Field of Search: 257/335, 257/342, 257/488, 257/491, 257/302, 257/329, 257/367, 257/E29.118, 257/E29.257, 257/E29.325
• US Class Current: 257/302
• CPC Class Codes: H01L 21/77 Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate electrically programmable read-only memories or multistep manufacturing processes therefor H10B69/00
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/19043 being a resistor

Abstract

In one embodiment, a transistor includes a pillar of semiconductor material arranged in a racetrack-shaped layout having a substantially linear section that extends in a first lateral direction and rounded sections at each end of the substantially linear section. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. First and second gate members respectively disposed in the first and second dielectric regions are separated from the pillar by a gate oxide having a first thickness in the substantially linear section. The gate oxide being substantially thicker at the rounded sections. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

Claims

1. A transistor comprising:

a pillar of semiconductor material arranged in a racetrack-shaped layout having a substantially linear section that extends in a first lateral direction and rounded sections at each end of the substantially linear section of the racetrack-shaped layout, a source region of a first conductivity type being disposed at or near a top surface of the pillar, and a body region of a second conductivity type being disposed in the pillar beneath the source region;

first and second dielectric regions disposed on opposite sides of the pillar, respectively, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar;

first and second field plates respectively disposed in the first and second dielectric regions;

first and second gate members respectively disposed in the first and second dielectric regions at or near the top surface of the pillar adjacent the body region, the first and second gate members being separated from the body region by a gate oxide having a first thickness in the substantially linear section of the racetrack-shaped layout, the gate oxide having a second thickness at the rounded sections, the second thickness being substantially larger than the first thickness.

2. The transistor of claim 1 wherein the first thickness is approximately 500 Å

.

3. The transistor of claim 1 wherein the second thickness is approximately 1 μ

m.

4. The transistor of claim 1 further comprising an extended drain region disposed in the pillar beneath the body region.

5. The transistor of claim 1 wherein a length of the substantially linear section in the first lateral direction is at least 30 times greater than a width of the racetrack-shaped layout, the width being in a second lateral direction orthogonal to the first lateral direction.

6. The transistor of claim 1 wherein the first and second gate members are completely insulated from the first and second field plates.

7. A transistor comprising:

a pillar of semiconductor material arranged in a racetrack-shaped layout having a substantially linear section that extends in a first lateral direction and rounded sections at each end of the substantially linear section of the racetrack-shaped layout;

first and second dielectric regions disposed on opposite sides of the pillar, respectively, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar;

first and second field plates respectively disposed in the first and second dielectric regions;

first and second gate members respectively disposed in the first and second dielectric regions at or near a top of the pillar, the first and second gate members being separated from the body region by a gate oxide having a first thickness in the substantially linear section of the racetrack-shaped layout, the gate oxide having a second thickness at the rounded sections, the second thickness being substantially larger than the first thickness.

8. The transistor of claim 7 wherein the first thickness is approximately 500 Å

.

9. The transistor of claim 7 wherein the second thickness is approximately 1 μ

m.

10. The transistor of claim 7 further comprising:

a body region disposed in the pillar beneath the source region; and

an extended drain region disposed in the pillar beneath the body region.

11. The transistor of claim 7 wherein a length of the substantially linear section in the first lateral direction is at least 30 times greater than a width of the racetrack-shaped layout, the width being a second lateral direction orthogonal to the first lateral direction.

12. A transistor comprising:

a racetrack-shaped pillar of semiconductor material having spaced-apart first and second linear portions that each extend in a first lateral direction, a first rounded portion of the racetrack-shaped pillar joining respective first ends of the first and second linear portions, a second rounded portion of the racetrack-shaped pillar joining respective second ends of the first and second linear portions;

first and second dielectric regions respectively disposed on opposite sides of the racetrack-shaped pillar, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar;

first and second field plates respectively disposed in the first and second dielectric regions;

first and second gate members respectively disposed in the first and second dielectric regions at or near a top of the first linear portion of the racetrack-shaped pillar;

third and fourth gate members respectively disposed in the first and second dielectric regions at or near a top of the second linear portion of the racetrack-shaped pillar; and

wherein the first, second, third and fourth gate members are each separated from the racetrack-shaped pillar by a gate oxide, opposite ends of the first, second, third and fourth gate members being terminated in the first lateral direction at or near the first and second rounded portions, respectively.

13. The transistor of claim 12 wherein the first, second, third and fourth gate members each comprise polysilicon.

14. The transistor of claim 12 wherein the gate oxide is approximately 500 Å

thick.

15. The transistor of claim 12 wherein a length of the substantially linear portion in the first lateral direction is at least 30 times greater than a distance separating the first and second substantially linear portions in a second lateral direction orthogonal to the first lateral direction.