Power device with trenches having wider upper portion than lower portion

• US 7,595,524 B2
• Filed: 03/17/2008
• Issued: 09/29/2009
• Est. Priority Date: 05/20/2003
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Herrick, Robert, Losee, Becky, Probst, Dean
• Primary Examiner(s): Tran, Long K
• Application Number:
  US12/049,996
• Publication Number:
  US 20080164519A1
• Time in Patent Office: 561 Days
• Field of Search: 257/E29.26, 257/E29.201, 257/E29.257, 257/E27.091, 257/302, 257/905, 257/311, 257/312, 257/313, 257/314, 257/315, 257/316, 257/317, 257/318, 257/319, 257/320, 257/321, 257/322, 257/323, 257/324, 257/325, 257/326, 257/330, 257/331, 257/332, 438/242, 438/245, 438/259, 438/270
• US Class Current: 257/302
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: Y10S 257/905 Plural dram cells share common contact or common trench

Abstract

A field effect transistor includes a plurality of trenches extending into a silicon layer. Each trench has upper sidewalls that fan out. Contact openings extend into the silicon layer between adjacent trenches such that each trench and an adjacent contact opening form a common upper sidewall portion. Body regions extend between adjacent trenches, and source regions extend in the body regions adjacent opposing sidewalls of each trench. The source regions have a conductivity type opposite that of the body regions.

Claims

1. A field effect transistor (FET) comprising:

a plurality of trenches extending into a silicon layer, each trench having upper sidewalls that fan out with a substantially vertically-extending top portion;

contact openings extending into the silicon layer between adjacent trenches such that each trench and an adjacent contact opening form a common upper sidewall portion corresponding to the substantially vertically-extending top portion;

body regions extending between adjacent trenches; and

source regions extending in the body regions adjacent opposing sidewalls of each trench, the source regions having a conductivity type opposite that of the body regions.

2. The FET of claim 1 further comprising a metal layer extending into each contact opening for contacting the regions along sidewalls of the source regions.

3. The FET of claim 1 wherein the entirety of each source region is disposed below a corresponding one of the common upper sidewalls.

4. The FET of claim 1 wherein each of the common upper sidewalls together with a sidewall of a corresponding source region form a sidewall of a contact opening.

5. The FET of claim 1 further comprising:

a gate electrode recessed in each trench;

a gate dielectric insulating the gate electrode from adjacent body regions; and

a dielectric region extending in each trench over the gate electrode.

6. The FET of claim 5 wherein the dielectric region has at least a portion that is fully contained within each trench, and sidewalls of the at least a portion of the dielectric region together with sidewalls of adjacent source regions form sidewalls of the contact openings.

7. The FET of claim 5 wherein the dielectric region has at least a portion that:

(a) is fully contained within each trench, and (b) defines upper portions of opposing sidewalls of the contact openings.

8. The FET of claim 5 wherein the dielectric region has a portion that:

(a) is fully contained within each trench, and (b) extends directly over at least a portion of an adjacent source region.

9. The FET of claim 1 wherein the source regions are self-aligned to the plurality of trenches.

10. The FET of claim 1 wherein the contact openings are self-aligned to the plurality of trenches.

11. A field effect transistor (FET) comprising:

an epitaxial layer of a first conductivity type extending over a substrate of the first conductivity type, the epitaxial layer having a lower doping concentration than the substrate;

a body region of a second conductivity type extending in an upper portion of the epitaxial layer, the second conductivity type being opposite the first conductivity type;

a plurality of trenches extending through the body region and terminating within the epitaxial layer below the body region, each trench having upper sidewalls that fan out with a substantially vertically-extending top portion;

contact openings extending into the body region between adjacent trenches such that each trench and an adjacent contact opening form a common upper sidewall corresponding to the substantially vertically-extending top portion; and

source regions of the first conductivity type extending in the body region adjacent opposing sidewalls of each trench.

12. The FET of claim 11 further comprising a metal layer extending into each contact opening for contacting the source regions along sidewalls of the source regions.

13. The FET of claim 11 wherein the entirety of each source region is disposed below a corresponding one of the common upper sidewalls.

14. The FET of claim 11 wherein each of the common upper sidewalls together with a sidewall of a corresponding source region form a sidewall of a contact opening.

15. The FET of claim 11 wherein the upper trench sidewalls that fan out also extend directly over at least a portion of corresponding source regions.

16. The FET of claim 11 further comprising:

a gate electrode recessed in each trench;

a gate dielectric insulating each gate electrode from adjacent body regions; and

a dielectric region extending over the gate electrode.

17. The FET of claim 15 wherein the dielectric region has at least a portion that is fully contained within each trench, sidewalls of the at least a portion of the dielectric region together with sidewalls of adjacent source regions form sidewalls of the contact openings.

18. The FET of claim 15 wherein the dielectric region has a portion that:

(a) is fully contained within each trench, and (b) extends directly over at least a portion of an adjacent source region.

19. The FET of claim 16 wherein the gate electrode is recessed in each trench below the upper trench sidewalls that fan out.

20. The FET of claim 11 wherein the source regions are self-aligned to the plurality of trenches.

21. The FET of claim 11 wherein the contact openings are self-aligned to the plurality of trenches.

22. A field effect transistor (FET) comprising:

an epitaxial layer of a first conductivity type extending over a substrate of the first conductivity type, the epitaxial layer having a lower doping concentration than the substrate;

a body region of a second conductivity type extending in an upper portion of the epitaxial layer, the second conductivity type being opposite the first conductivity type;

a plurality of trenches extending through the body region and terminating within the epitaxial layer below the body region, each trench having upper sidewalls that fan out with a substantially vertically-extending top portion;

contact openings extending into the body region between adjacent trenches such that each trench and an adjacent contact opening form a common upper sidewall portion corresponding to the substantially vertically-extending top portion;

a gate electrode recessed in each trench;

a gate dielectric insulating each gate electrode from adjacent body regions;

a dielectric region extending over the gate electrode;

source regions of the first conductivity type extending in the body region adjacent opposing sidewalls of each trench;

a highly doped region of the second conductivity type extending in the body region below each contact opening; and

a metal layer extending over the dielectric region, the metal layer further extending into each contact opening for contacting the highly doped region along a bottom of each contact opening and for contacting the source regions along sidewalls of the source regions.

23. The FET of claim 22 wherein the entirety of each source region is disposed below a corresponding one of the common upper sidewall portions.

24. The FET of claim 22 wherein each of the common upper sidewall portions together with a sidewall of a corresponding source region form a sidewall of a contact opening.

25. The FET of claim 22 wherein the dielectric region has at least a portion that is fully contained within each trench, sidewalls of the at least a portion of the dielectric region together with sidewalls of adjacent source regions form sidewalls of the contact openings.

26. The FET of claim 22 wherein the dielectric region has at least a portion that is:

(a) fully contained within each trench, and (b) defines upper portions of opposing sidewalls of the contact openings.

27. The FET of claim 22 wherein the upper trench sidewalls that fan out also extend directly over at least a portion of corresponding source regions.

28. The FET of claim 22 wherein the dielectric region has a portion that:

(a) is fully contained within each trench, and (b) extends directly over at least a portion of an adjacent source region.

29. The FET of claim 22 wherein the gate electrode is recessed in each trench below the upper trench sidewalls that fan out.

30. The FET of claim 22 wherein the source regions are self-aligned to the plurality of trenches.

31. The FET of claim 22 wherein the contact openings are self-aligned to the plurality of trenches.