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Semiconductor integrated circuit devices having upper pattern aligned with lower pattern molded by semiconductor substrate and methods of forming the same

  • US 7,595,529 B2
  • Filed: 07/18/2008
  • Issued: 09/29/2009
  • Est. Priority Date: 02/21/2007
  • Status: Active Grant
First Claim
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1. A semiconductor integrated circuit device comprising:

  • a semiconductor substrate having an isolation layer;

    an upper pattern disposed in a predetermined region of the semiconductor substrate, the upper pattern protruding upward from a top surface of the isolation layer and extending downward from the top surface of the isolation layer; and

    a lower pattern including a buried plug disposed below the top surface of the isolation layer to be surrounded by the upper pattern through the predetermined region of the semiconductor substrate to contact the upper pattern and a buried capping pattern disposed on the buried plug and protruding from the top surface of the isolation layer to surround the upper pattern,wherein the upper pattern has the same width on the buried plug along a direction toward the top surface of the isolation layer.

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