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Periphery design for charge balance power devices

  • US 7,595,542 B2
  • Filed: 03/13/2006
  • Issued: 09/29/2009
  • Est. Priority Date: 03/13/2006
  • Status: Active Grant
First Claim
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1. A charge balance semiconductor power device, comprising:

  • an active area comprising strips of first conductivity type pillars and strips of second conductivity type pillars arranged in an alternating manner so as to form PN junctions therebetween, the strips of first conductivity type pillars and strips of second conductivity type pillars extending along a length of the active area; and

    a non-active perimeter region surrounding the active area, comprising at least one ring of the first conductivity type surrounding the active area,wherein one end of at least one of the strips of first conductivity type pillars extending immediately adjacent an edge of the active area terminates at a straight line at which one end of each of the remainder of the strips of first conductivity type pillars also terminate, the straight line extending perpendicular to the length of the active area along which the strips of first and second conductivity type pillars extend, wherein the end of the at least one of the strips of first conductivity type pillars is structurally identical to the end of each of the remainder of the strips of first conductivity type pillars, and wherein every two adjacent strips of first conductivity type pillars in the active region are spaced from one another by a first spacing, the straight line defining a first edge of the active area, wherein the first edge of the active area is spaced from the at least one ring of the first conductivity type by a second spacing, wherein the second spacing is smaller than the first spacing to thereby increase breakdown voltage in the non-active perimeter region.

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