Periphery design for charge balance power devices

• US 7,595,542 B2
• Filed: 03/13/2006
• Issued: 09/29/2009
• Est. Priority Date: 03/13/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Higgs, Jason, Lee, Jaegil, Kocon, Christopher Boguslaw, Park, Chanho, Yedinak, Joseph A.
• Primary Examiner(s): Coleman; W. David
• Assistant Examiner(s): Kim; Su C
• Application Number:
  US11/375,683
• Publication Number:
  US 20070210341A1
• Time in Patent Office: 1,296 Days
• Field of Search: 257/288, 257/328, 257/331, 257/487, 257/488, 257/489, 257/490, 257/491, 257/492, 257/493, 257/494, 257/495, 257/E29.005, 257/E29.024, 257/E29.026, 257/E29.027, 438/140
• US Class Current: 257/495
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A charge balance semiconductor power device comprises an active area having strips of p pillars and strips of n pillars arranged in an alternating manner, the strips of p and n pillars extending along a length of the active area. A non-active perimeter region surrounds the active area, and includes at least one p ring surrounding the active area. One end of at last one of the strips of p pillars extending immediately adjacent an edge of the active area terminates at a substantially straight line at which one end of each of the remainder of the strips of p pillars also end. The straight line extends perpendicular to the length of the active area along which the strips of n and p pillars extend.

Claims

1. A charge balance semiconductor power device, comprising:

an active area comprising strips of first conductivity type pillars and strips of second conductivity type pillars arranged in an alternating manner so as to form PN junctions therebetween, the strips of first conductivity type pillars and strips of second conductivity type pillars extending along a length of the active area; and

a non-active perimeter region surrounding the active area, comprising at least one ring of the first conductivity type surrounding the active area,

wherein one end of at least one of the strips of first conductivity type pillars extending immediately adjacent an edge of the active area terminates at a straight line at which one end of each of the remainder of the strips of first conductivity type pillars also terminate, the straight line extending perpendicular to the length of the active area along which the strips of first and second conductivity type pillars extend, wherein the end of the at least one of the strips of first conductivity type pillars is structurally identical to the end of each of the remainder of the strips of first conductivity type pillars, and wherein every two adjacent strips of first conductivity type pillars in the active region are spaced from one another by a first spacing, the straight line defining a first edge of the active area, wherein the first edge of the active area is spaced from the at least one ring of the first conductivity type by a second spacing, wherein the second spacing is smaller than the first spacing to thereby increase breakdown voltage in the non-active perimeter region.

2. The charge balance semiconductor power device of claim 1 wherein the second spacing is less than or equal to about one-half of the first spacing.

3. The charge balance semiconductor power device of claim 1 wherein the non-active perimeter region comprises a plurality of rings of the first conductivity type, every two adjacent rings of the first conductivity type being spaced from one another by a distance equal to the first spacing.

4. The charge balance semiconductor power device of claim 1 wherein the at least one ring of the first conductivity type is rectangular or square in shape with rounded corners.

5. The charge balance semiconductor power device of claim 1 wherein the at least one ring of the first conductivity type is rectangular or square in shape with sharp corners.

6. The charge balance semiconductor power device of claim 1 wherein the strips of first conductivity type pillars and the strips of second conductivity type pillars abut at one end the at least one ring of the first conductivity type.

7. The charge balance semiconductor power device of claim 1 wherein the charge balance semiconductor power device is a vertically-conducting power device.

8. The charge balance semiconductor power device of claim 1 wherein the first conductivity type is p type and second conductivity type is n type.

9. A charge balance semiconductor power device, comprising:

an active area comprising vertically-extending strips of first conductivity type pillars and vertically-extending strips of second conductivity type pillars arranged in an alternating manner, every two adjacent strips of first conductivity type pillars being spaced from one another by a first spacing; and

a non-active perimeter region surrounding the active area, comprising at least two horizontally-extending strips of first conductivity type pillars and at least two vertically-extending strips of first conductivity type pillars, the at least two horizontally-extending strips of first conductivity type pillars being spaced from one another by a second spacing, and the at least two vertically-extending strips of first conductivity type pillars in the non-active perimeter region being spaced from one another by a spacing substantially equal to the second spacing, an end of each of the at least two horizontally-extending strips of first conductivity type pillars being spaced from a corresponding one of the at least two vertically-extending strips of first conductivity type pillars in the non-active perimeter region by a third spacing, wherein the second spacing is greater than the third spacing.

10. The charge balance semiconductor power device of claim 9 wherein the second spacing is substantially equal to the first spacing.

11. The charge balance semiconductor power device of claim 9 wherein an end of the vertically-extending strips of first conductivity type pillars in the active area is spaced from one of the at least two horizontally-extending strips of first conductivity type pillars by a spacing substantially equal to the third spacing.

12. The charge balance semiconductor power device of claim 9 wherein each of the at least two vertically-extending strips of first conductivity type pillars in the non-active perimeter region extends past an end of a corresponding one of the at least two horizontally-extending strips of first conductivity type pillars by a predetermined distance.

13. The charge balance semiconductor power device of claim 9 wherein the third spacing is substantially equal to one-half the second spacing.

14. The charge balance semiconductor power device of claim 9 wherein the first conductivity type is p type and second conductivity type is n type.