Logic cell array and bus system

• US 7,595,659 B2
• Filed: 10/08/2001
• Issued: 09/29/2009
• Est. Priority Date: 10/09/2000
• Status: Active Grant

• Current Assignee: Scientia Sol Mentis AG (PACT XPP Schweiz AG)
• Original Assignee: Pact XPP Technologies, AG
• Inventors: Vorbach, Martin, Ehlers, Gerd, Nückel, Armin, Reichardt, Dirk, May, Frank, Lier, Frank, Rao, Prashant, Baumgarte, Volker, Oertel, Jens
• Primary Examiner(s): Tan; Vibol
• Application Number:
  US10/398,546
• Publication Number:
  US 20040128474A1
• Time in Patent Office: 2,913 Days
• Field of Search: 326 38- 41, 708/501, 708/620
• US Class Current: 326/39
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points.

Claims

1. A reconfigurable chip, comprising:

a plurality of data modification units that are interconnected at least two-dimensionally and runtime reconfigurable in function and interconnection, wherein at least some of the data modification units are arithmetic logic cells that each;

has three inputs A, B, and C adapted for feeding to the respective arithmetic logic cell respective ones of three data words A, B, and C on respective ones of the three inputs A, B, and C; and

is adapted for performing within the respective arithmetic logic cell an operation of the data word A×

the data word B+ the data word C;

registers adapted for receiving output data of one of the plurality of modification units and feeding the output data back for further processing in the modification unit;

registers adapted for delaying arrival of data at respective ones of the plurality of modification units to synchronize the arrival of the data with an arrival of other data at the respective modification units; and

multiplexers adapted for selectively bypassing registers of the reconfigurable chip to allow for an orderly data processing in runtime-delayed data;

wherein the chip is one of a processing chip and a Field Programmable Gate Array chip.

2. The reconfigurable chip of claim 1, wherein each of at least some of the arithmetic logic cells has functional units that include at least one multiplier and one adding stage connected downstream of the at least one multiplier.

3. The reconfigurable chip of claim 1, wherein a digital DSP signal processor is formed by the arithmetic logic cells.

48. The reconfigurable chip of claim 1, wherein the operation includes adding the data word C to the product of the data word A×

the data word B.

4. A reconfigurable processing chip, comprising:

a plurality of data modification units, wherein;

at least some of the data modification units are arithmetic logic cells that each;

has three inputs A, B, and C adapted for feeding to the respective arithmetic logic cell respective ones of three data words A, B, and C on respective ones of the three inputs A, B, and C; and

is adapted for performing within the respective arithmetic logic cell an operation of the data word A×

the data word B+ the data word C; and

each of at least some of the arithmetic logic cells has functional units that include at least one multiplier and one adding stage connected downstream of the at least one multiplier; and

a bypass line in at least one of the arithmetic logic cells that has the functional units, wherein the bypass line is adapted for allowing data to pass by at least one of the functional units of the at least one arithmetic logic cell.

5. The reconfigurable processing chip of claim 4, wherein the bypass line is adapted for selectively allowing data words to bypass.

6. A reconfigurable processing chip, comprising:

a plurality of data modification units, wherein at least some of the data modification units are arithmetic logic cells that each;

has three inputs A, B, and C adapted for feeding to the respective arithmetic logic cell respective ones of three data words A, B, and C on respective ones of the three inputs A, B, and C; and

is adapted for performing within the respective arithmetic logic cell an operation of the data word A ×

the data word B + the data word C; and

a register adapted for providing a configurable register delay of a data relay in an arithmetic logic cell.

7. The reconfigurable processing chip of claim 6, wherein the data relay delaying register is adapted for a register delay of data words that are at least one of modified and linked in functional units of the arithmetic logic cells.

8. The reconfigurable processing chip of claim 6, wherein the data relay delaying register is adapted for a register delay of a data relay of unmodified data words.

9. The reconfigurable processing chip of claim 6, wherein the register for the data relay delay is adapted for a configurable data relay delay.

10. The reconfigurable processing chip of claim 6, wherein the register is a deep register adapted for functioning as an intermediate memory.

11. The reconfigurable processing chip of claim 6, wherein the register is adapted for being connected into and removed from a data path.

12. The reconfigurable processing chip of any one of claims 4, 5, 6, and 11, wherein the reconfigurable processing chip is a Field Programmable Gate Array (FPGA).

13. A Field Programmable Gate Array chip, comprising:

a plurality of data modification units, wherein at least some of the data modification units are arithmetic logic cells that each;

has three inputs A, B, and C adapted for feeding to the respective arithmetic logic cell respective ones of three data words A, B, and C on respective ones of the three inputs A, B, and C; and

is adapted for performing within the respective arithmetic logic cell an operation of the data word A ×

the data word B + the data word C; and

a multiplexer provided at an output of an arithmetic logic cell and adapted for connecting a result from the arithmetic logic cell to a bus.

14. The Field Programmable Gate Array chip of claim 13, wherein a width of the output is greater than a width of two data words to be linked.

15. A logic cell for a Field Programmable Gate Array chip, the logic cell adapted for performing an arithmetic-multiplicative operation on operands using the logic cell, comprising:

three inputs A, B, C adapted for feeding to the logic cell respective ones of three data words A, B, and C onthe three inputs A, B, C;

wherein;

the logic cell is adapted for;

performing within the logic cell an operation of the data word A ×

the data word B + the data word C;

outputting data to a register and feeding the output data from the register back for further processing in the logic cell; and

synchronously receiving a plurality of data, some of the plurality of data being received from a register that delays the some of the plurality of data in order to effect the synchronization of the some of the plurality of data with other of the plurality of data.

16. A runtime-configurable logic cell for use in a reconfigurable processing chip, the runtime-configurable logic cell comprising:

a multiplier; and

an adder connected behind the multiplier;

wherein;

for two data word inputs A and B provided to the multiplier, the adder is adapted for adding a data word C for optimizing a function of A×

B+C; and

the logic cell is adapted for;

outputting data to a register and feeding the output data back from the register for further processing in the logic cell; and

synchronously receiving a plurality of data, some of the plurality of data being received from a register that delays the some of the plurality of data in order to effect the synchronization of the some of the plurality of data with other of the plurality of data.

49. The runtime-configurable logic cell of any one of claims 16 and 19, wherein the reconfigurable processing chip is a Field Programmable Gate Array (FPGA).

17. A runtime-configurable logic cell for use in one of a reconfigurable processing chip and a Field Programmable Gate Array chip, the runtime-configurable logic cell comprising:

a multiplier;

an adder; and

three data inputs adapted for data of two the data inputs to be fed to the multiplier and data of the third data input to be fed to the adder;

wherein the logic cell is adapted for;

outputting data to a register and feeding back the output data from the register into the logic cell; and

synchronously receiving a plurality of data, some of the plurality of data being received from a register that delays the some of the plurality of data in order to effect the synchronization of the some of the plurality of data with other of the plurality of data.

18. The runtime-configurable logic cell of claim 17, wherein the multiplier is adapted for being connectable to the adder for a result output by the multiplier to be fed to an input of the adder.

19. A runtime-configurable logic cell for use in a reconfigurable processing chip, the runtime-configurable logic cell comprising:

a multiplier;

an adder; and

three data inputs adapted for data of two the data inputs to be fed to the multiplier and data of the third data input to be fed to the adder;

wherein;

the multiplier is adapted for being connectable to the adder for a result output by the multiplier to be fed to an input of the adder; and

a result output by the logic cell is wider than its inputs and corresponds to a width of the result output by the multiplier.

20. A runtime-configurable logic cell for use in a Field Programmable Gate Array chip, the runtime-configurable logic cell, comprising:

a multiplier;

an adder;

three data inputs adapted for data of two the data inputs to be fed to the multiplier and data of the third data input to be fed to the adder;

a register; and

a multiplexer adapted for connecting the register to and removing the register from a data relay path.

21. The runtime-configurable logic cell of claim 20, wherein the register is a deep register adapted for functioning as an intermediate memory.

22. The runtime-configurable logic cell of claim 21, wherein the register is a first-in-first-out (FIFO) register.

23. The runtime-configurable logic cell of claim 22, wherein the FIFO register is adapted for a multi-clock-pulse intermediate storage of data.

24. A runtime-configurable logic cell array for use in a reconfigurable processing chip, the runtime-configurable logic cell array comprising:

logic cells, at least one of the logic cells comprising;

a multiplier;

an adder connected downstream of the multiplier;

at least one first register adapted for receiving output data from at least one of the multiplier and the adder and feeding the output data back for further processing in the logic cell;

at least further registers adapted for delaying arrival of data at the at least one of the logic cells to synchronize the arrival of the data with an arrival of other data at the at least one of the logic cells; and

multiplexers adapted for selectively bypassing at least some of said first and further registers of the at least one of the logic cells to allow for an orderly data processing in runtime-delayed data; and

programmable gate arrays surrounding the logic cells.

25. The runtime-configurable logic cell array of claim 24, further comprising:

register stages adapted for being configurably assigned to the logic cells.

50. The runtime-configurable logic cell array of claim 24, wherein the reconfigurable processing chip is a Field Programmable Gate Array (FPGA).

26. A Field Programmable Gate Array chip, comprising:

a plurality of data modification units, wherein at least some of the data modification units are arithmetic logic cells that each;

has three inputs A, B, and C adapted for feeding to the respective arithmetic logic cell respective ones of three data words A, B, and C on respective ones of the three inputs A, B, and C; and

is adapted for performing within the respective arithmetic logic cell an operation of the data word A×

the data word B+ the data word C; and

registers adapted for delaying arrival of data at respective ones of the plurality of data modification units to synchronize the arrival of the data with an arrival of other data at the respective modification units.

27. The Field Programmable Gate Array chip of claim 26, wherein the registers include a data relay delaying register that is adapted for a register delay of data words that are at least one of modified and linked in functional units of the arithmetic logic cells.

28. The Field Programmable Gate Array chip of claim 27, wherein the data relay delaying register is adapted for a register delay of a data relay of unmodified data words.

29. The Field Programmable Gate Array chip of claim 26, wherein the Field Programmable Gate Array chip is at least two-dimensionally interconnected.

30. The Field Programmable Gate Array chip of claim 26, wherein the Field Programmable Gate Array chip is reconfigurable in function and interconnection.

31. The Field Programmable Gate Array chip of claim 26, wherein the Field Programmable Gate Array chip is runtime reconfigurable in function.

32. The Field Programmable Gate Array chip of claim 26, wherein, for each of at least some of the arithmetic logic cells, a data storage device is adapted for providing data, locally written to the data storage device, for local modification.

33. The Field Programmable Gate Array chip of claim 26, wherein registers are adapted for receiving output data of one of the plurality of data modification units and for feeding the output data to an input of an element of the one of the plurality of modification units.

34. The Field Programmable Gate Array chip of claim 26, wherein the registers include a data relay delaying register that is adapted for register delay of unmodified data words.

35. The Field Programmable Gate Array chip of claim 26, wherein a width of an output of two linked data words is greater than the width of each of the two linked data words.

36. The Field Programmable Gate Array chip of claim 26, wherein the arithmetic logic cells are adapted for synchronously receiving a plurality of data, some of the plurality of data being receivable from a register that delays the some of the plurality of data in order to effect the synchronization of the some of the plurality of data with other of the plurality of data.

37. The Field Programmable Gate Array chip of claim 26, wherein the registers include a first-in-first-out register.

38. The Field Programmable Gate Array chip of claim 26, further comprising:

multiplexers adapted for selectively bypassing registers of the Field Programmable Gate Array chip to allow for an orderly data processing in runtime delayed data.

39. The Field Programmable Gate Array chip of claim 26, wherein a multiplier is adapted for connection to an adder for a result output by the multiplier to be fed to an input of the adder.

40. The Field Programmable Gate Array chip of claim 26, further comprising:

programmable gate arrays in a vicinity of the arithmetic logic cells for at least one of receiving data from the arithmetic logic cells and transmitting data to the arithmetic logic cells in order to combine data.

41. The Field Programmable Gate Array chip of claim 26, wherein the Field Programmable Gate Array chip is one of a processor, a data flow processor, a digital processor, and a programmable logic chip.

42. The Field Programmable Gate Array chip of claim 26, wherein the registers include a register that is a deep register having more than one register stage adapted for functioning as an intermediate memory.

43. The Field Programmable Gate Array chip of claim 26, wherein the registers include a register that is adapted for being configurably connected into and removed from a data path.

44. The Field Programmable Gate Array chip of claim 26, wherein:

registers are adapted for delaying arrival of data in respective ones of functional elements within the modification units to synchronize the arrival of the data with an arrival of other data at the respective functional elements; and

the functional elements are at least one of arithmetically and logically combining elements.

45. The Field Programmable Gate Array chip of claim 26, wherein a FIFO register of the Field Programmable Gate Array chip is adapted for a multi-clock-pulse intermediate storage of data.

46. A runtime-configurable logic cell array for use in one of a reconfigurable processing chip and a field programmable logic chip, the runtime-configurable logic cell comprising:

logic cells, at least one of the logic cells comprising;

a multiplier;

an adder connected downstream of the multiplier;

at least one first register adapted for receiving output data from at least one of the multiplier and the adder and feeding the output data back for further processing in the logic cell;

at least two further registers adapted for delaying arrival of data at the at least one of the logic cells to synchronize the arrival of the data with an arrival of other data at the at least one of the logic cells; and

multiplexers adapted for selectively bypassing at least some of said first and further registers of the at least one of the logic cells to allow for an orderly data processing in runtime-delayed data; and

programmable gate arrays in a vicinity of the logic cells.

47. The runtime-configurable logic cell array of claim 46, wherein the logic cells are adapted for exchanging with each other data for combinatorial purposes.

51. The runtime-configurable logic cell array of claim 46, wherein the runtime-configurable logic cell array is for use in the reconfigurable processing chip and the reconfigurable processing chip is a Field Programmable Gate Array (FPGA).

52. A reconfigurable processing chip, comprising:

a plurality of configurable cells arranged in a two-dimensional structure; and

a configurable network interconnecting the configurable cells;

wherein;

each of at least some of the configurable cells is an arithmetic cell that comprises;

at least three operand data inputs for receiving operands A, B, C, from the configurable network, at least one of the operand data inputs comprising an input register;

at least one arithmetic unit processing the operands and producing result data; and

at least one result output for transmitting said result data of the arithmetic unit to the configurable network, at least one of the at least one result output comprising an output register; and

the at least one arithmetic unit;

comprises at least two function units, the at least two function units including (a) at least one multiplier and (b) at least one adder; and

is adapted to produce the result data by computing a function A times B plus C (A×

B+C) on the operands.

53. The reconfigurable processing chip according to claim 52, wherein, within the arithmetic cell, result data of at least one result register and produced by the at least one arithmetic unit is fed back into the arithmetic cell for further processing.

54. The reconfigurable processing chip according to claim 52, wherein, within the arithmetic cell, at least some of the function units are bypassable.

55. The reconfigurable processing chip according to any one of claims 52 and 53, wherein the result data of the arithmetic cell is wider than a width of the received operands.

56. The reconfigurable processing chip according to any one of claims 52 and 53, wherein at least some of the registers have increased depth.

57. The reconfigurable processing chip according to any one of claims 52 and 53, wherein at least some of the registers are FIFOs.

58. The reconfigurable processing chip according to any one of claims 52, 53, and 54, wherein the arithmetic cells comprise at least one intermediate result register located between (a) the at least one multiplier and (b) one of he at least one adder.

59. The reconfigurable processing chip according to any one of claims 52, 53, and 54, wherein at least one of the at least one input register and at least one of the at least one output register comprise a related multiplexer for configurable insertion or bypassing of the respective register.

60. The reconfigurable processing chip according to claim 56, wherein at least one of the at least one input register and at least one of the at least one output register comprise a related multiplexer for configurable insertion or bypassing of the respective register.

61. The reconfigurable processing chip according to claim 57, wherein at least one of the at least one input register and at least one of the at least one output register comprise a related multiplexer for configurable insertion or bypassing of the respective register.

62. The reconfigurable processing chip according to claim 58, wherein at least one of the at least one input register, at least one of the at least one output register, and at least one of the intermediate result registers comprise a related multiplexer for configurable insertion or bypassing of the respective register.

63. The reconfigurable processing chip according to any one of claims 52, 53, and 54, wherein the reconfigurable processing chip is a field programmable gate array (FPGA) chip.

64. The reconfigurable processing chip according to claim 58, wherein the reconfigurable processing chip is a field programmable gate array (FPGA) chip.

65. The reconfigurable processing chip according to claim 59, wherein the reconfigurable processing chip is a field programmable gate array (FPGA) chip.

66. The reconfigurable processing chip according to claim 60, wherein the reconfigurable processing chip is a field programmable gate array (FPGA) chip.

67. The reconfigurable processing chip according to claim 61, wherein the reconfigurable processing chip is a field programmable gate array (FPGA) chip.

68. The reconfigurable processing chip according to claim 62, wherein the reconfigurable processing chip is a field programmable gate array (FPGA) chip.

69. A reconfigurable processing chip comprising:

a plurality of configurable cells arranged in a two-dimensional structure; and

a configurable network connecting the configurable cells;

wherein;

each of at least some of the configurable cells is an arithmetic cell that comprises;

at least four operand data inputs A, DO, C, and D2 for receiving operands from the configurable network, at least one of the operand inputs comprising an input register;

at least one arithmetic unit processing the operands and producing result data, the at least one arithmetic unit comprising at least three function units, the functions units including (a) at least one multiplier and (b) at least two adders; and

at least one result output for transmitting said result data of the arithmetic unit to the configurable network;

at least one of the at least one result output comprises an output register;

the arithmetic unit is adapted to produce the result data by computing an intermediate result Q1 by adding operands of D0 and D2 (Q1=D0+D2) in a first Add stage and computing a result of an operand of A times Q1 plus an operand of C (A×

Q1+C) in a subsequent MultiplyAdd stage one the operand data; and

the intermediate result Q1 is configurably connectable to the operand input D0.

70. The reconfigurable chip according to claim 69, wherein, within the arithmetic cell, at least one multiplexer is located between the first Add stage for computing Q1=D0+D2 and the subsequent MultiplyAdd stage for computing A×

Q1+C for selectively bypassing the first Add stage.

71. The reconfigurable chip according to any of claims 69 and 70, wherein, within the arithmetic cell, at least some of the function units are bypassable.

72. The reconfigurable chip according to claim 71, wherein, within the arithmetic cell, result data of at least one result register and produced by the at least one arithmetic unit is fed back into the arithmetic cell for further processing.

73. The reconfigurable chip according to any one of claims 69, 70, 71, and 72, wherein the result data of the arithmetic cell is wider than a width of the received operands.

74. The reconfigurable chip according to any one of claims 69, 70, 71, and 72, wherein at least some of the registers have increased depth.

75. The reconfigurable chip according to any one of claims 69, 70, 71, and 72, wherein at least some of the registers are FIFOs.

76. The reconfigurable chip according to any one of claims 69, 70, 71, and 72, wherein the arithmetic cells comprise, at least one intermediate result register located between at least one adder and a subsequent function unit.

77. The reconfigurable chip according to any one of claims 69, 70, 71, and 72, wherein at least one of the at least one input register and at least one of the at least one output register comprise a related multiplexer for configurable insertion or bypassing of the respective register.

78. The reconfigurable processing chip according to claim 74, wherein at least one of the at least one input register and at least one of the at least one output register comprise a related multiplexer for configurable insertion or bypassing of the respective register.

79. The reconfigurable processing chip according to claim 75, wherein at least one of that at least one input register and at least one of the at least one output register comprise a related multiplexer for configurable insertion or bypassing of the respective register.

80. The reconfigurable processing chip according to claim 76, wherein at least one of at least one input register, at least one of the at least one output register, and at least one of the at least one intermediate result register comprise a related multiplexer for configurable insertion or bypassing of the respective register.

81. The reconfigurable chip according to any one of claims 69, 70, 72, 78, 79, and 80, wherein the reconfigurable processing chip is a field programmable gate array (FPGA) chip.

82. The reconfigurable processing chip according to claim 71, wherein the reconfigurable processing chip is a field programmable gate array (FPGA) chip.

83. The reconfigurable processing chip according to claim 76, wherein the reconfigurable processing chip is a field programmable gate array (FPGA) chip.

84. The reconfigurable processing chip according to claim 77, wherein the reconfigurable processing chip is a field programmable gate array (FPGA) chip.

85. A reconfigurable processing chip, comprising:

a plurality of configurable cells arranged in a two-dimensional structure; and

a configurable network connecting the configurable cells;

wherein;

each of at least some of the configurable cells is an arithmetic cell that comprises;

at least three operand data inputs for receiving respective operands, A, B, C, from the configurable network;

at least one of the at least three operand inputs comprising an input register;

at least one arithmetic unit processing the operands and producing result data, the at least one arithmetic unit comprising at least two function units, the fUnction units including (a) at least one multiplier and (b) at least one adder;

the at least one arithmetic unit is adapted to produce the result data by computing a fUnction A times B plus C (A×

B+C) on the operand data;

at least one result output for transmitting said result data of the arithmetic unit to the configurable network, at least one of the at least one result output comprising an output register; and

an interconnection arrangement for selectively at least one of(a) chaining at least two of the function units for transferring at least one output data of at least one of said function units as input data to at least another one of said function units, (b) bypassing at least one of the function units, and (c) feeding at least one of said operands (A, B, C) as input to at least one of said function units.

86. The reconfigurable processing chip according to claim 85, wherein, within the arithmetic cell, result data of at least one result register and produced by the at least one arithmetic unit is fed back into the arithmetic cell for further processing.

87. The reconfigurable processing chip according to claim 85, wherein, within the arithmetic cell, at least some of the function units are bypassable

88. The reconfigurable processing chip according to claim 85 or 86, wherein at least some of the registers have increased depth.

89. The reconfigurable processing chip according to claim 85 or 86, wherein at least some of the registers are FIFOs.

90. The reconfigurable processing chip according to any one of the claims 85, 86, and 87, wherein the arithmetic cells comprise at least one intermediate result register located between (a) the at least one multiplier and (b) one of the at least one adder.

91. The reconfigurable processing chip according to any one of the claims 85, 86, and 87, wherein at least one of the at least one input register and at least one of the at least one output register comprise a related multiplexer for configurable insertion or bypassing of the respective register.

92. The reconfigurable processing chip according to claim 88, wherein at least one of the at least one input register and at least one of the at least one output register comprise a related multiplexer for configurable insertion or bypassing of the respective register.

93. The reconfigurable processing chip according to claim 89, wherein at least one of the at least one input register and at least one of the at least one output register comprise a related multiplexer for configurable insertion or bypassing of the respective register.

94. The reconfigurable processing chip according to claim 90, wherein at least one of the at least one input register, at least one of the at least one output register, and at least one of the intermediate result registers comprise a related multiplexer for configurable insertion or bypassing of the respective register.

95. The reconfigurable processing chip according to claim 90, wherein the reconfigurable processing chip is a field programmable gate array (FPGA) chip.

96. The reconfigurable processing chip according to claim 91, wherein the reconfigurable processing chip is a field programmable gate array (FPGA) chip.

97. The reconfigurable processing chip according to claim 92, wherein the reconfigurable processing chip is a field programmable gate array (FPGA) chip.

98. The reconfigurable processing chip according to claim 93, wherein the reconfigurable processing chip is a field programmable gate array (FPGA) chip.

99. The reconfigurable processing chip according to claim 94, wherein the reconfigurable processing chip is a field programmable gate array (FPGA) chip.

100. The reconfigurable processing chip according to claim 85, wherein:

at least one of the arithmetic cells comprises further operand data inputs for receiving operands D0 and D2; and

for each of at least one of said at least one arithmetic unit of said at least one of the arithmetic cells, the arithmetic unit;

includes at least one multiplier and at least two adders; and

is adapted to produce the result data by computing an intermediate result Q1 by adding operands D0 and D2 (Q1=D0+D2) in a first Add stage and computing a result A times Q1 plus C (A×

Q1+C) in a subsequent MultiplyAdd stage on the operand data.

101. The reconfigurable processing chip according to claim 100, wherein, within an arithmetic cell, result data of at least one result register is fed back into the arithmetic cell for further processing.

102. The reconfigurable processing chip according to claim 100, wherein, within an arithmetic cell, at least some of the function units are bypassable.

103. The reconfigurable processing chip according to claim 85 or 100, wherein at least some of the registers have increased depth.

104. The reconfigurable processing chip according to any one of the claims 100, 101 and 102, wherein at least some of the registers are FIFOs.

105. The reconfigurable processing chip according to any one of the claims 100, 101, 102 and 103, wherein the arithmetic cells comprise at least one intermediate result register located between an adder and a multiplier.

106. The reconfigurable processing chip according to claim 103, wherein the reconfigurable processing chip is a field programmable gate array (FPGA) chip.

107. The reconfigurable processing chip according to claim 104, wherein the reconfigurable processing chip is a field programmable gate array (FPGA) chip.

108. The reconfigurable processing chip according to claim 105, wherein the reconfigurable processing chip is a field programmable gate array (FPGA) chip.

109. The reconfigurable processing chip according to claim 85, wherein, for each of at least one of said at least one arithmetic unit, the arithmetic unit includes at least one multiplier and at least two adders.

110. The reconfigurable processing chip according to claim 109, wherein, within the arithmetic cell, result data of at least one result register is fed back into the arithmetic cell for further processing.

111. The reconfigurable processing chip according to claim 109, wherein, within the arithmetic cell, at least some of the function units are bypassable.

112. The reconfigurable processing chip according to any one of the claims 85, 86, 87, 100, 101, 102, 109, 110, and 111, whereinthereconfigurableprocessing chip is a field programmable gate array (FPGA) chip.

113. A reconfigurable processing chip, comprising:

a plurality of configurable cells arranged in a two-dimensional structure; and

a configurable network connecting the configurable cells;

wherein each of at least some of the configurable cells is an arithmetic cell that comprises;

at least four operand data inputs A, B, C, and D for receiving operands from the configurable network;

at least one of the at least four operand inputs comprising an input register;

at least one arithmetic unit processing the operands and producing result data, the at least one arithmetic unit comprising at least three function units, the function units including (a) at least one multiplier and (b) at least two adders; and

at least one result output for transmitting said result data of the arithmetic unit to the configurable network, at least one of the at least one result output comprising an output register.

114. The reconfigurable processing chip according to claim 113, wherein, within the arithmetic cell, at least some of the function units are bypassable.

115. The reconfigurable processing chip according to claim 114, wherein, within the arithmetic cell, result data of at least one result register and produced by the at least one arithmetic unit is fed back into the arithmetic cell for further processing.

116. The reconfigurable processing chip according to any one of claims 113, 114 and 115, wherein a result of the arithmetic cell is wider than a width of at least one of the received operands.

117. The reconfigurable processing chip according to any one of claims 113, 114 and 115, wherein at least some of the registers have increased depth.

118. The reconfigurable processing chip according to any one of claims 113, 114 and 115, wherein at least some of the registers are FIFOs.

119. The reconfigurable processing chip according to any one of claims 113, 114 and 115, wherein the arithmetic cell comprises at least one intermediate result register located between at least one adder and a subsequent function unit.

120. The reconfigurable processing chip according to any one of claims 113, 114 and 115, wherein at least one of the input registers and at least one of the output registers comprise a related multiplexer for configurable insertion or bypassing of the respective register.

121. The reconfigurable processing chip according to claim 117, wherein at least one of the at least one input register and at least one of the at least one output register comprise a related multiplexer for configurable insertion or bypassing of the respective register.

122. The reconfigurable processing chip according to claim 118, wherein at least one of the at least one input register and at least one of the at least one output register comprise a related multiplexer for configurable insertion or bypassing of the respective register.

123. The reconfigurable processing chip according to claim 119, wherein at least one of the at least one input register, at least one of the at least one output register, and at least one of the intermediate result registers comprise a related multiplexer for configurable insertion or bypassing of the respective register.

124. The reconfigurable processing chip according to any one of the claims 113, 114, and 115, wherein the reconfigurable processing chip is a field programmable gate array (FPGA) chip.

125. The reconfigurable processing chip according to claim 119, wherein the reconfigurable processing chip is a field programmable gate array (FPGA) chip.

126. The reconfigurable processing chip according to claim 120, wherein the reconfigurable processing chip is a field programmable gate array (FPGA) chip.

127. The reconfigurable processing chip according to claim 121, wherein the reconfigurable processing chip is a field programmable gate array (FPGA) chip.

128. The reconfigurable processing chip according to claim 122, wherein the reconfigurable processing chip is a field programmable gate array (FPGA) chip.

129. The reconfigurable processing chip according to claim 123, wherein the reconfigurable processing chip is a field programmable gate array (FPGA) chip.