Low voltage differential signaling drivers including branches with series resistors

• US 7,595,661 B2
• Filed: 12/06/2005
• Issued: 09/29/2009
• Est. Priority Date: 12/17/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Jin-hyun
• Primary Examiner(s): Barnie; Rexford N
• Assistant Examiner(s): WHITE, DYLAN C
• Application Number:
  US11/295,353
• Publication Number:
  US 20060132179A1
• Time in Patent Office: 1,393 Days
• Field of Search: 326/68, 326/82, 326/83, 326/86, 326/112, 326/115, 326/119, 327/333
• US Class Current: 326/82
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end
• CPC Class Codes: H04L 5/16 Half-duplex systems; Simplex/duplex switching; Transmission of break signals non-automatically inverting the direction of transmission

Abstract

A low voltage differential signal driver includes first and second current sources, a first branch and a second branch. The first branch includes at least two transistors and at least two resistors between them that are all connected in series between the first and second current sources, to define a first node between adjacent resistors that is configured to transmit and receive differential signals. The second branch also includes at least two transistors and at least two resistors between them that also are all connected in series between the first and second current sources, to define a second node between adjacent resistors that is also configured to transmit and receive differential signals.

Claims

1. A low voltage differential signaling driver comprising:

first and second current sources;

a first branch, which comprises at least two transistors and at least two resistors therebetween that are all connected in series between the first and second current sources to define a first node between adjacent resistors that is configured to transmit and receive a first signal;

a second branch, which comprises at least two transistors and at least two resistors therebetween that also are all connected in series between the first and second current sources to define a second node between adjacent resistors that is also configured to transmit and receive a second signal; and

a control switch connected between the first branch and the second branch, which controls the transmission and reception of the first and second signals,

wherein the first signal and the second signal are differential signals;

wherein the first branch comprises;

a first transistor which has a first controlled electrode connected to the first current source and has a controlling electrode to which data is input;

a first resistor which has one end connected to a second controlled electrode of the first transistor and has the other end connected to the first node;

a second transistor which has a first controlled electrode connected to the second current source and has a controlling electrode to which the data is input; and

a second resistor which has one end connected to the first node and has the other end connected to a second controlled electrode of the second transistor;

wherein the second branch comprises;

a third transistor which has a first controlled electrode connected to the first current source and has a controlling electrode to which inverted data is input, the inverted data having a logic level opposite to the logic level of the data;

a third resistor which has one end connected to a second controlled electrode of the third transistor and has the other end connected to the second node;

a fourth transistor which has a first controlled electrode connected to the second current source and has a controlling electrode to which the inverted data is input; and

a fourth resistor which has one end connected to the second node and has the other end connected to a second controlled electrode of the fourth transistor; and

wherein the control switch is connected between a third node and a fourth node, the third node connecting the first transistor and the first resistor and the fourth node connecting the third transistor and the third resistor.

2. The low voltage differential signaling driver of claim 1, wherein if the data has a second logic level, the first and fourth transistors are turned on, and the second and third transistors are turned off, and if the data has a first logic level, the second and third transistors are turned on, and the first and fourth transistors are turned off.

3. The low voltage differential signaling driver of claim 2, wherein the first and second nodes are connected to first and second transmission lines having load resistance connected thereto and wherein if the data has the second logic level, a result of summing up a total resistance of a current path formed between the first current source and the first node and a total resistance of a current path formed between the second node and the second current source is equal to the load resistance.

4. The low voltage differential signaling driver of claim 2, wherein the first and second nodes are connected to first and second transmission lines having load resistance connected thereto and wherein if the data has the first logic level, a result of summing up a total resistance of a current path formed between the first current source and the second node and a total resistance of a current path formed between the first node and the second current source is equal to the load resistance.

5. The low voltage differential signaling driver of claim 1, wherein the first and second nodes are connected to first and second transmission lines having load resistance connected thereto and wherein if the load resistance is 2 Z, each of the first through fourth resistors has a resistance of 0.9 Z.

6. The low voltage differential signaling driver of claim 1, wherein if differential signals are input to the low voltage differential signaling driver via the first and second nodes, all of the first through fourth transistors are turned off, and the control switch is turned on.

7. A low voltage differential signaling driver comprising:

a driving unit which is configured to output a pull-down signal having a first common mode voltage level and a pull-up signal having a second common mode voltage level in response to a control signal, a clock signal, and data;

a transmission unit which is configured to output an output differential signal via transmission lines in response to the pull-up signal and the pull-down signal output from the driving unit; and

a reception unit which is configured to receive an input differential signal via the transmission lines,

wherein the transmission unit comprises;

first and second current sources;

a first branch, which comprises at least two transistors and at least two resistors therebetween that are all connected in series between the first and second current sources to define a first node between adjacent resistors that is configured to transmit and receive a first signal;

a second branch, which comprises at least two transistors and at least two resistors therebetween that also are all connected in series between the first and second current sources to define a second node between adjacent resistors that is also configured to transmit and receive a second signal; and

a control switch connected between the first branch and the second branch which controls a transmission and reception of the first and second signals,

wherein the first signal and the second signal are differential signals and

wherein the driving unit comprises;

a first controller which is configured to control the logic levels of the pull-down signal and an inverted pull-down signal based on a logic level of the data in response to the control signal and the clock signal; and

a second controller which is configured to control the logic levels of the pull-up signal and an inverted pull-up signal based on the logic level of the data in response to an inverted control signal and an inverted clock signal.

8. The low voltage differential signaling driver of claim 7, wherein the first common mode voltage level is a voltage level suitable for controlling an NMOS transistor at high speed, the second common mode voltage level is a voltage level suitable for controlling a PMOS transistor at high speed, and the first common mode voltage level is higher than the second common mode voltage level.

9. The low voltage differential signaling driver of claim 8, wherein the first branch comprises:

a first transistor which has a first controlled electrode connected to the first current source and has a controlling electrode to which data is input;

a first resistor which has one end connected to a second controlled electrode of the first transistor and has the other end connected to the first node;

a second transistor which has a first controlled electrode connected to the second current source and has a controlling electrode to which the data is input; and

a second resistor which has one end connected to the first node and has the other end connected to a second controlled electrode of the second transistor, and wherein the second branch further comprises;

a third transistor which has a first controlled electrode connected to the first current source and has a controlling electrode to which inverted data is input, the inverted data having a logic level opposite to the logic level of the data;

a third resistor which has one end connected to a second controlled electrode of the third transistor and has the other end connected to the second node;

a fourth transistor which has a first controlled electrode connected to the second current source and has a controlling electrode to which the inverted data is input; and

a fourth resistor which has one end connected to the second node and has the other end connected to a second controlled electrode of the fourth transistor.

10. The low voltage differential signaling driver of claim 9, wherein if the data has a second logic level, the first and fourth transistors are turned on, and the second and third transistors are turned off, and if the data has a first logic level, the second and third transistors are turned on, and the first and fourth transistors are turned off.

11. The low voltage differential signaling driver of claim 9, wherein if the data has the second logic level, a result of summing up a total resistance of a current path formed between the first current source and the first node and a total resistance of a current path formed between the second node and the second current source is equal to a load resistance that is connected to the transmission lines.

12. The low voltage differential signaling driver of claim 9, wherein if the data has the first logic level, a result of summing up a total resistance of a current path formed between the first current source and the second node and a total resistance of a current path formed between the first node and the second current source is equal to a load resistance that is connected to the transmission lines.

13. The low voltage differential signaling driver of claim 9, wherein if a load resistance that is connected to the transmission lines is 2 Z, each of the first through fourth resistors has a resistance of 0.9 Z.

14. The low voltage differential signaling driver of claim 9 further comprising:

a control switch which is provided between a third node and a fourth node, the third node connecting the first transistor and the first resistor and the fourth node connecting the third transistor and the third resistor.

15. The low voltage differential signaling driver of claim 14, wherein if differential signals are input to the low voltage differential signaling driver via the transmission lines, all of the first through fourth transistors are turned off, and the control switch is turned on.

16. The low voltage differential signaling driver of claim 7, wherein the first controller comprises:

a pull-down signal generator which is configured to generate the pull-down signal whose logic level is opposite to the logic level of the data in response to the control signal and the clock signal; and

an inverted pull-down signal generator which is configured to generate the inverted pull-down signal whose logic level is identical to the logic level of the data in response to the control signal and the clock signal.

17. The low voltage differential signaling driver of claim 16, wherein the pull-down signal generator comprises:

a first control resistor which is connected between a power supply voltage and a first control node;

a first control transistor, the controlled electrodes of which are connected between the first control node and a ground voltage and the controlling electrode of which is connected to the control signal; and

second and third control transistors, the controlled electrodes of which are connected to each other in series between the first control node and the ground voltage and the controlling electrodes of which are connected to the clock signal and the data, respectively, and

the inverted pull-down signal generator comprising;

a second control resistor which is connected between the power supply voltage and a second control node;

a fourth control transistor, the controlled electrodes of which are which is connected between the second control node and the ground voltage and the controlling electrode of which is connected to the control signal; and

fifth and sixth control transistors, the controlled electrodes of which are connected to each other in series between the second control node and the ground voltage and the controlling electrodes of which are connected to the clock signal and inverted data, respectively.

18. The low voltage differential signaling driver of claim 16, wherein the second controller comprises:

a pull-up signal generator which is configured to generate the pull-up signal whose logic level is identical to the logic level of the data in response to the inverted control signal and the inverted clock signal; and

an inverted pull-up signal generator which is configured to generate the inverted pull-up signal whose logic level is opposite to the logic level of the data in response to the inverted control signal and the inverted clock signal.

19. The low voltage differential signaling driver of claim 18, wherein the pull-up signal generator comprises:

first and second inverted control transistors, the controlled electrodes of which are connected in series between the power supply voltage and a first inverted control node and the controlling electrodes of which are connected to the inverted data and the inverted clock signal, respectively;

a third inverted control transistor, the controlled electrodes of which are connected between the power supply voltage and the first inverted control node and the controlling electrode of which is connected to the inverted control signal; and

a third control resistor which is connected between the first inverted control node and the ground voltage, and wherein

the inverted pull-up signal generator comprises;

fourth and fifth inverted control transistors, the controlled electrodes of which are connected in series between the power supply voltage and a second inverted control node and the controlling electrodes of which are connected to the data and the inverted clock signal, respectively;

a sixth inverted control transistor, the controlled electrodes of which are connected between the power supply voltage and the second inverted control node and the controlling electrode of which is connected to the inverted control signal; and

a fourth control resistor which is connected between the second inverted control node and the ground voltage.

20. A data communication system comprising:

first and second low voltage differential signaling drivers which are connected to each other via transmission lines and transmit data to or receive data from each other via the transmission lines,

wherein the first low voltage differential signaling driver comprises;

a control switch, which controls the transmission and reception of the data; and

a driving unit, which is configured to reduce signal reflections using termination resistance which is same as load resistance of the second low voltage differential signaling driver and is configured to enhance the speed of transmitting data by controlling the logic level of the data in response to the control switch, and the second low voltage differential signaling driver has same structure as the first low voltage differential signaling driver;

wherein the first low voltage differential signaling driver comprises;

the driving unit which is configured to output a pull-down signal having a first common mode voltage level and a pull-up signal having a second common mode voltage level in response to a control signal, a clock signal, and data;

a transmission unit which is configured to output an output differential signal via the transmission lines in response to the pull-up signal and the pull-down signal output from the driving unit; and

a reception unit which is configured to receive an input differential signal from outside of the low voltage differential signaling driver via the transmission lines,

wherein the transmission unit comprises;

first and second current sources;

a first branch, which comprises at least two transistors and at least two resistors therebetween that are all connected in series between the first and second current sources to define a first node between adjacent resistors that is configured to transmit and receive differential signals; and

a second branch, which comprises at least two transistors and at least two resistors therebetween that also are all connected in series between the first and second current sources to define a second node between adjacent resistors that is also configured to transmit and receive differential signals; and

wherein the driving unit comprises;

a first controller which is configured to control the logic levels of the pull-down signal and an inverted pull-down signal based on the logic level of the data in response to the control signal and the clock signal; and

a second controller which is configured to control the logic levels of the pull-up signal and an inverted pull-up signal based on the logic level of the data in response to an inverted control signal and an inverted clock signal.

21. The data communication system of claim 20, wherein the first common mode voltage level is a voltage level suitable for controlling an NMOS transistor at high speed, the second common mode voltage level is a voltage level suitable for controlling a PMOS transistor at high speed, and the first common mode voltage level is higher than the second common mode voltage level.

22. The low voltage differential signaling driver of claim 20, wherein the first controller comprises:

a pull-down signal generator which is configured to generate the pull-down signal whose logic level is opposite to the logic level of the data in response to the control signal and the clock signal; and

an inverted pull-down signal generator which is configured to generate the inverted pull-down signal whose logic level is identical to the logic level of the data in response to the control signal and the clock signal.

23. The data communication system of claim 22, wherein the pull-down signal generator comprises:

a first control resistor which is connected between a power supply voltage and a first control node;

a first control transistor, the controlled electrodes of which are connected between the first control node and a ground voltage and the controlling electrode of which is connected to the control signal; and

second and third control transistors, the controlled electrodes of which are connected to each other in series between the first control node and the ground voltage and the controlling electrodes of which are connected to the clock signal and the data, respectively, and

the inverted pull-down signal generator comprising;

a second control resistor which is connected between the power supply voltage and a second control node;

a fourth control transistor, the controlled electrodes of which are connected between the second control node and the ground voltage and the controlling electrode of which is connected to the control signal; and

fifth and sixth control transistors, the controlled electrodes of which are connected to each other in series between the second control node and the ground voltage and the controlling electrodes of which are connected to the clock signal and inverted data, respectively.

24. The data communication system of claim 20, wherein the second controller comprises:

a pull-up signal generator which is configured to generate the pull-up signal whose logic level is identical to the logic level of the data in response to the inverted control signal and the inverted clock signal; and

an inverted pull-up signal generator which is configured to generate the inverted pull-up signal whose logic level is opposite to the logic level of the data in response to the inverted control signal and the inverted clock signal.

25. The data communication system of claim 24, wherein the pull-up signal generator comprises:

first and second inverted control transistors, the controlled electrodes of which are connected in series between the power supply voltage and a first inverted control node and the controlling electrodes of which are connected to the inverted data and the inverted clock signal, respectively;

a third inverted control transistor, the controlled electrodes of which are connected between the power supply voltage and the first inverted control node and the controlling electrode of which is connected to the inverted control signal; and

a third control resistor which is connected between the first inverted control node and the ground voltage, and wherein

the inverted pull-up signal generator comprises;

fourth and fifth inverted control transistors the controlled electrodes of which are connected in series between the power supply voltage and a second inverted control node and the controlling electrodes of which are connected to the data and the inverted clock signal, respectively;

a sixth inverted control transistor, the controlled electrodes of which are connected between the power supply voltage and the second inverted control node and the controlling electrode of which is connected to the inverted control signal; and

a fourth control resistor which is connected between the second inverted control node and the ground voltage.

26. A data communication method for a low voltage differential signaling driver which comprises first and second branches and a control switch which controls the reception of a differential signal and transmits and receives the differential signal via transmission lines in response to data, the data communication method comprising:

determining whether to transmit or receive a differential signal;

turning off the control switch if it is determined to transmit the differential signal;

selectively turning on transistors included in the first and second branches according to the voltage level of data input to the low voltage differential signaling driver;

outputting the differential signal to the transmission lines using a current path formed by the transistors that are turned on;

turning on the control switch if it is determined to receive the differential signal; and

receiving the differential signal via the transmission lines.

27. The data communication method of claim 26, wherein the first branch comprises:

at least two transistors and at least two resistors therebetween that are all connected in series between first and second current sources, to define a first node between adjacent resistors that is configured to be connected to one of the transmission lines; and

wherein the second branch comprises at least two transistors and at least two resistors therebetween that are all connected in series between the first and second current sources, to define a second node between adjacent resistors that is configured to be connected to another of the transmission lines.

28. The data communication method of claim 27, wherein if the data has the second logic level, a result of summing up a total resistance of a current path formed between the first current source and the first node and a total resistance of a current path formed between the second node and the second current source is equal to a load resistance which is connected to the transmission lines.

29. The data communication method of claim 27, wherein if the data has the first logic level, a result of summing up a total resistance of a current path formed between the first current source and the second node and a total resistance of a current path formed between the first node and the second current source is equal to a load resistance which is connected to the transmission lines.

30. The data communication method of claim 27, wherein if the control switch is turned on, all of the transistors included in the first and second branches are turned off.

31. The data communication method of claim 27, wherein the selectively turning on of the transistors included in the first and second branches according to the voltage level of the input data, comprises:

controlling the voltage level of the input data; and

applying the input data whose voltage level has been controlled to the transistors included in the first and second branches.

32. The data communication method of claim 31, wherein in the controlling of the voltage level of the input data, the voltage level of the input data is controlled based on a common mode voltage level of the transistors included in the first and second branches.