Low voltage differential signaling drivers including branches with series resistors
First Claim
1. A low voltage differential signaling driver comprising:
- first and second current sources;
a first branch, which comprises at least two transistors and at least two resistors therebetween that are all connected in series between the first and second current sources to define a first node between adjacent resistors that is configured to transmit and receive a first signal;
a second branch, which comprises at least two transistors and at least two resistors therebetween that also are all connected in series between the first and second current sources to define a second node between adjacent resistors that is also configured to transmit and receive a second signal; and
a control switch connected between the first branch and the second branch, which controls the transmission and reception of the first and second signals,wherein the first signal and the second signal are differential signals;
wherein the first branch comprises;
a first transistor which has a first controlled electrode connected to the first current source and has a controlling electrode to which data is input;
a first resistor which has one end connected to a second controlled electrode of the first transistor and has the other end connected to the first node;
a second transistor which has a first controlled electrode connected to the second current source and has a controlling electrode to which the data is input; and
a second resistor which has one end connected to the first node and has the other end connected to a second controlled electrode of the second transistor;
wherein the second branch comprises;
a third transistor which has a first controlled electrode connected to the first current source and has a controlling electrode to which inverted data is input, the inverted data having a logic level opposite to the logic level of the data;
a third resistor which has one end connected to a second controlled electrode of the third transistor and has the other end connected to the second node;
a fourth transistor which has a first controlled electrode connected to the second current source and has a controlling electrode to which the inverted data is input; and
a fourth resistor which has one end connected to the second node and has the other end connected to a second controlled electrode of the fourth transistor; and
wherein the control switch is connected between a third node and a fourth node, the third node connecting the first transistor and the first resistor and the fourth node connecting the third transistor and the third resistor.
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Accused Products
Abstract
A low voltage differential signal driver includes first and second current sources, a first branch and a second branch. The first branch includes at least two transistors and at least two resistors between them that are all connected in series between the first and second current sources, to define a first node between adjacent resistors that is configured to transmit and receive differential signals. The second branch also includes at least two transistors and at least two resistors between them that also are all connected in series between the first and second current sources, to define a second node between adjacent resistors that is also configured to transmit and receive differential signals.
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Citations
32 Claims
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1. A low voltage differential signaling driver comprising:
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first and second current sources; a first branch, which comprises at least two transistors and at least two resistors therebetween that are all connected in series between the first and second current sources to define a first node between adjacent resistors that is configured to transmit and receive a first signal; a second branch, which comprises at least two transistors and at least two resistors therebetween that also are all connected in series between the first and second current sources to define a second node between adjacent resistors that is also configured to transmit and receive a second signal; and a control switch connected between the first branch and the second branch, which controls the transmission and reception of the first and second signals, wherein the first signal and the second signal are differential signals; wherein the first branch comprises; a first transistor which has a first controlled electrode connected to the first current source and has a controlling electrode to which data is input; a first resistor which has one end connected to a second controlled electrode of the first transistor and has the other end connected to the first node; a second transistor which has a first controlled electrode connected to the second current source and has a controlling electrode to which the data is input; and a second resistor which has one end connected to the first node and has the other end connected to a second controlled electrode of the second transistor; wherein the second branch comprises; a third transistor which has a first controlled electrode connected to the first current source and has a controlling electrode to which inverted data is input, the inverted data having a logic level opposite to the logic level of the data; a third resistor which has one end connected to a second controlled electrode of the third transistor and has the other end connected to the second node; a fourth transistor which has a first controlled electrode connected to the second current source and has a controlling electrode to which the inverted data is input; and a fourth resistor which has one end connected to the second node and has the other end connected to a second controlled electrode of the fourth transistor; and wherein the control switch is connected between a third node and a fourth node, the third node connecting the first transistor and the first resistor and the fourth node connecting the third transistor and the third resistor. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A low voltage differential signaling driver comprising:
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a driving unit which is configured to output a pull-down signal having a first common mode voltage level and a pull-up signal having a second common mode voltage level in response to a control signal, a clock signal, and data; a transmission unit which is configured to output an output differential signal via transmission lines in response to the pull-up signal and the pull-down signal output from the driving unit; and a reception unit which is configured to receive an input differential signal via the transmission lines, wherein the transmission unit comprises; first and second current sources; a first branch, which comprises at least two transistors and at least two resistors therebetween that are all connected in series between the first and second current sources to define a first node between adjacent resistors that is configured to transmit and receive a first signal; a second branch, which comprises at least two transistors and at least two resistors therebetween that also are all connected in series between the first and second current sources to define a second node between adjacent resistors that is also configured to transmit and receive a second signal; and a control switch connected between the first branch and the second branch which controls a transmission and reception of the first and second signals, wherein the first signal and the second signal are differential signals and wherein the driving unit comprises; a first controller which is configured to control the logic levels of the pull-down signal and an inverted pull-down signal based on a logic level of the data in response to the control signal and the clock signal; and a second controller which is configured to control the logic levels of the pull-up signal and an inverted pull-up signal based on the logic level of the data in response to an inverted control signal and an inverted clock signal. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A data communication system comprising:
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first and second low voltage differential signaling drivers which are connected to each other via transmission lines and transmit data to or receive data from each other via the transmission lines, wherein the first low voltage differential signaling driver comprises; a control switch, which controls the transmission and reception of the data; and a driving unit, which is configured to reduce signal reflections using termination resistance which is same as load resistance of the second low voltage differential signaling driver and is configured to enhance the speed of transmitting data by controlling the logic level of the data in response to the control switch, and the second low voltage differential signaling driver has same structure as the first low voltage differential signaling driver; wherein the first low voltage differential signaling driver comprises; the driving unit which is configured to output a pull-down signal having a first common mode voltage level and a pull-up signal having a second common mode voltage level in response to a control signal, a clock signal, and data; a transmission unit which is configured to output an output differential signal via the transmission lines in response to the pull-up signal and the pull-down signal output from the driving unit; and a reception unit which is configured to receive an input differential signal from outside of the low voltage differential signaling driver via the transmission lines, wherein the transmission unit comprises; first and second current sources; a first branch, which comprises at least two transistors and at least two resistors therebetween that are all connected in series between the first and second current sources to define a first node between adjacent resistors that is configured to transmit and receive differential signals; and a second branch, which comprises at least two transistors and at least two resistors therebetween that also are all connected in series between the first and second current sources to define a second node between adjacent resistors that is also configured to transmit and receive differential signals; and wherein the driving unit comprises; a first controller which is configured to control the logic levels of the pull-down signal and an inverted pull-down signal based on the logic level of the data in response to the control signal and the clock signal; and a second controller which is configured to control the logic levels of the pull-up signal and an inverted pull-up signal based on the logic level of the data in response to an inverted control signal and an inverted clock signal. - View Dependent Claims (21, 22, 23, 24, 25)
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26. A data communication method for a low voltage differential signaling driver which comprises first and second branches and a control switch which controls the reception of a differential signal and transmits and receives the differential signal via transmission lines in response to data, the data communication method comprising:
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determining whether to transmit or receive a differential signal; turning off the control switch if it is determined to transmit the differential signal; selectively turning on transistors included in the first and second branches according to the voltage level of data input to the low voltage differential signaling driver; outputting the differential signal to the transmission lines using a current path formed by the transistors that are turned on; turning on the control switch if it is determined to receive the differential signal; and receiving the differential signal via the transmission lines. - View Dependent Claims (27, 28, 29, 30, 31, 32)
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Specification