Logic process DRAM

• US 7,596,011 B1
• Filed: 02/26/2007
• Issued: 09/29/2009
• Est. Priority Date: 06/28/2000
• Status: Expired due to Fees

• Current Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Lee, Winston, Sutardja, Sehat, Lee, Peter
• Primary Examiner(s): Nguyen; Viet Q
• Application Number:
  US11/710,818
• Time in Patent Office: 946 Days
• Field of Search: 365/63, 365/72, 365/51, 365/189.02, 365/230.02
• US Class Current: 365/63
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H10B 12/482 Bit lines

Abstract

An integrated circuit device comprises a plurality of bit line pairs. First and second bit lines are aligned with each other in an end-to-end arrangement. The first and second bit lines are arranged consecutively adjacent to one another, respectively. A plurality of word lines is associated with the first bit lines and the second bit lines. A first array includes the first bit lines and first associated ones of the plurality of word lines, and wherein a second array includes the second bit lines and second ones of the plurality of associated word lines. A first plurality of multiplexers communicates with two adjacent bits lines within one of the first and second arrays. The first array operates as a sense array and the second array operates as a reference array when at least one of the plurality of word lines is active in the first array.

Claims

1. An integrated circuit device comprising:

a plurality of bit line pairs, wherein first and second bit lines within each of the plurality of bit line pairs are aligned with each other in an end-to-end arrangement, wherein the first bit lines are arranged consecutively adjacent to one another, and wherein the second bit lines are arranged consecutively adjacent to one another;

a plurality of word lines associated with the first bit lines and the second bit lines, wherein a first array includes the first bit lines and first associated ones of the plurality of word lines, and wherein a second array includes the second bit lines and second ones of the plurality of associated word lines; and

a first plurality of multiplexers, each communicating with two adjacent bit lines within one of the first and second arrays, wherein each of the first plurality of multiplexers selectively outputs one of the two adjacent bit lines,

wherein the first array operates as a sense array and the second array operates as a reference array when at least one of the plurality of word lines is active in the first array.

2. The integrated circuit device of claim 1, further comprising a plurality of memory cells, wherein, for each word line, bit lines that are not associated with the plurality of memory cells act as a shield between bit lines that are associated with the plurality of memory cells.

3. The integrated circuit device of claim 1 further comprising:

a second plurality of multiplexers; and

memory including a plurality of sense amplifiers, each communicating with one of the first plurality of multiplexers associated with two adjacent first bit lines of the first array and one of the second plurality of multiplexers associated with two corresponding adjacent second bit lines of the second array.

4. The integrated circuit device of claim 1, further comprising memory including a second plurality of multiplexers in communication with a voltage source input and with two adjacent bit lines within one of the first and second arrays.

5. The integrated circuit device of claim 1, further comprising memory including:

a first interconnect layer; and

a second interconnect layer, wherein each bit line is associated with both the first and second interconnect layers.

6. The integrated circuit device of claim 5, wherein the first interconnect layer comprises a first metal layer, and the second interconnect layer comprises a second metal layer.

7. The integrated circuit device of claim 5, wherein the first interconnect layer comprises a metal layer, and the second interconnect layer comprises a polysilicon layer.

8. The integrated circuit device of claim 5, wherein the first interconnect layer comprises a polysilicon layer, and the second interconnect layer comprises a metal layer.

9. The integrated circuit device of claim 1, further comprising memory.

10. The integrated circuit device of claim 9, wherein the memory is manufactured using a logic process.

11. The integrated circuit device of claim 9, wherein the memory is manufactured using a DRAM process.

23. The integrated circuit device of claim 1, wherein each of the first plurality of multiplexers selectively outputs the one of the two adjacent bit lines by selecting between the two adjacent bit lines.

24. The integrated circuit device of claim 1, further comprising a second plurality of multiplexers, wherein the first plurality of multiplexers communicates with the first array and the second plurality of multiplexers communicates with the second array, and wherein each of the second plurality of multiplexers communicates with two adjacent bit lines within the second array.

25. The integrated circuit device of claim 24, further comprising a plurality of sense amplifiers that each directly communicates with one of the first plurality of multiplexers and one of the second plurality of multiplexers, respectively.

12. A method comprising:

aligning first and second bit lines within each of a plurality of bit line pairs with each other in an end-to-end arrangement;

arranging the first bit lines consecutively adjacent to one another;

arranging the second bit lines consecutively adjacent to one another;

associating a plurality of word lines with the first bit lines and the second bit lines, wherein a first array includes the first bit lines and first associated ones of the plurality of word lines, and wherein a second array includes the second bit lines and second ones of the plurality of associated word lines;

providing a first plurality of multiplexers, each communicating with two adjacent bit lines within one of the first and second arrays, wherein each of the first plurality of multiplexers selectively outputs one of the two adjacent bit lines; and

operating the first array as a sense array and the second array as a reference array when at least one of the plurality of word lines is active in the first array.

13. The method of claim 12, further comprising:

providing a plurality of memory cells; and

for each word line, using bit lines that are not associated with the plurality of memory cells as a shield between bit lines that are associated with the plurality of memory cells.

14. The method of claim 12, further comprising providing memory including a plurality of sense amplifiers, each communicating with one of the first plurality of multiplexers associated with two adjacent first bit lines of the first array and one of a second plurality of multiplexers associated with two corresponding adjacent second bit lines of the second array.

15. The method of claim 12, further comprising providing memory including a second plurality of multiplexers in communication with a voltage source input and with two adjacent bit lines within one of the first and second arrays.

16. The method of claim 12, further comprising:

providing memory including first and second interconnect layers; and

associating each bit line with both the first and second interconnect layers.

17. The method of claim 16, wherein the first interconnect layer comprises a first metal layer, and the second interconnect layer comprises a second metal layer.

18. The method of claim 16, wherein the first interconnect layer comprises a metal layer, and the second interconnect layer comprises a polysilicon layer.

19. The method of claim 16, wherein the first interconnect layer comprises a polysilicon layer, and the second interconnect layer comprises a metal layer.

20. The method of claim 12, further comprising providing memory.

21. The method of claim 20, further comprising manufacturing the memory using a logic process.

22. The method of claim 20, further comprising manufacturing the memory using a DRAM process.