Logic process DRAM
First Claim
1. An integrated circuit device comprising:
- a plurality of bit line pairs, wherein first and second bit lines within each of the plurality of bit line pairs are aligned with each other in an end-to-end arrangement, wherein the first bit lines are arranged consecutively adjacent to one another, and wherein the second bit lines are arranged consecutively adjacent to one another;
a plurality of word lines associated with the first bit lines and the second bit lines, wherein a first array includes the first bit lines and first associated ones of the plurality of word lines, and wherein a second array includes the second bit lines and second ones of the plurality of associated word lines; and
a first plurality of multiplexers, each communicating with two adjacent bit lines within one of the first and second arrays, wherein each of the first plurality of multiplexers selectively outputs one of the two adjacent bit lines,wherein the first array operates as a sense array and the second array operates as a reference array when at least one of the plurality of word lines is active in the first array.
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Abstract
An integrated circuit device comprises a plurality of bit line pairs. First and second bit lines are aligned with each other in an end-to-end arrangement. The first and second bit lines are arranged consecutively adjacent to one another, respectively. A plurality of word lines is associated with the first bit lines and the second bit lines. A first array includes the first bit lines and first associated ones of the plurality of word lines, and wherein a second array includes the second bit lines and second ones of the plurality of associated word lines. A first plurality of multiplexers communicates with two adjacent bits lines within one of the first and second arrays. The first array operates as a sense array and the second array operates as a reference array when at least one of the plurality of word lines is active in the first array.
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Citations
25 Claims
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1. An integrated circuit device comprising:
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a plurality of bit line pairs, wherein first and second bit lines within each of the plurality of bit line pairs are aligned with each other in an end-to-end arrangement, wherein the first bit lines are arranged consecutively adjacent to one another, and wherein the second bit lines are arranged consecutively adjacent to one another; a plurality of word lines associated with the first bit lines and the second bit lines, wherein a first array includes the first bit lines and first associated ones of the plurality of word lines, and wherein a second array includes the second bit lines and second ones of the plurality of associated word lines; and a first plurality of multiplexers, each communicating with two adjacent bit lines within one of the first and second arrays, wherein each of the first plurality of multiplexers selectively outputs one of the two adjacent bit lines, wherein the first array operates as a sense array and the second array operates as a reference array when at least one of the plurality of word lines is active in the first array. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 23, 24, 25)
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12. A method comprising:
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aligning first and second bit lines within each of a plurality of bit line pairs with each other in an end-to-end arrangement; arranging the first bit lines consecutively adjacent to one another; arranging the second bit lines consecutively adjacent to one another; associating a plurality of word lines with the first bit lines and the second bit lines, wherein a first array includes the first bit lines and first associated ones of the plurality of word lines, and wherein a second array includes the second bit lines and second ones of the plurality of associated word lines; providing a first plurality of multiplexers, each communicating with two adjacent bit lines within one of the first and second arrays, wherein each of the first plurality of multiplexers selectively outputs one of the two adjacent bit lines; and operating the first array as a sense array and the second array as a reference array when at least one of the plurality of word lines is active in the first array. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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Specification