System and method for transmitting data packets in a computer system having a memory hub architecture

• US 7,596,641 B2
• Filed: 05/10/2006
• Issued: 09/29/2009
• Est. Priority Date: 08/31/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joe, James, Ralph
• Primary Examiner(s): Tsai; Henry W. H.
• Assistant Examiner(s): Nam; Hyun
• Application Number:
  US11/432,017
• Publication Number:
  US 20060271720A1
• Time in Patent Office: 1,238 Days
• Field of Search: 710/36, 710/20
• US Class Current: 710/36
• CPC Class Codes: G06F 13/1642 with request queuing

Abstract

A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled an upstream link. The upstream reception port receives the data packets from downstream memory hubs. The system further includes a bypass bus coupled to the upstream reception port. The bypass bus transports the data packets from the upstream reception port. The system further includes a temporary storage coupled to the upstream reception port and configured to receive the data packets from the upstream reception port. The system further includes a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the temporary storage, or the bypass bus. The system further includes a breakpoint logic circuit coupled to the bypass multiplexer and configured to switch the bypass multiplexer to selectively connect the upstream transmission port to either one of the core logic circuit, the bypass bus, or the temporary storage. The system further includes a local memory coupled to the core logic circuit and operable to receive and send the data packets to the core logic circuit.

Claims

1. A memory hub operable to control communications for an upstream link, the memory hub comprising:

a transmission port operable to transmit data to the upstream link;

a reception port operable to receive first data for the upstream link;

core logic operable to receive local data for the upstream link;

a bypass multiplexer coupled to the transmission port, the reception port, and the core logic, the bypass multiplexer operable to selectively couple the upstream link to the reception port or the core logic; and

breakpoint logic coupled to the bypass multiplexer operable to identify a breakpoint at an end of a packet and, responsive to the identification, operable to couple a control signal to the bypass multiplexer before the end of the packet is received by the reception port to initiate a switch between the reception port and the core logic.

2. The memory hub of claim 1, wherein the breakpoint logic implements a switching algorithm.

3. The memory hub of claim 1, wherein the breakpoint logic is operable to determine a type of packet received at the reception port.

4. The memory hub of claim 1, wherein the bypass multiplexer is coupled to the reception port through a bypass bus.

5. The memory hub of claim 1, further comprising a temporary memory coupled to the reception port and the breakpoint logic, the breakpoint logic further operable to selectively couple the upstream logic to the temporary memory, the temporary memory operable to store data received at the reception port when the reception port is not coupled to the upstream link.

6. The memory hub of claim 5, wherein the temporary memory comprises a FIFO memory.

7. The memory hub of claim 6, wherein the temporary memory further comprises a data buffer, the data buffer operable to store further data received at the reception port when the FIFO memory is full.

8. The memory hub of claim 1, further comprising a clock domain change circuit coupled between the core logic and the bypass multiplexer.

9. A memory system comprising:

a memory controller;

a memory hub coupled to the controller by an upstream link, the memory hub operable to control communications for the upstream link, the memory hub comprising;

a transmission port coupled to the upstream link;

a reception port operable to receive first data for the upstream link;

core logic operable to receive local data for the upstream link;

a bypass multiplexer coupled to the transmission port, the reception port, and the core logic, the bypass multiplexer operable to selectively couple the upstream link to the reception port or to a local memory; and

breakpoint logic coupled to the bypass multiplexer operable to identify a breakpoint at an end of a packet and, responsive to the identification, operable to couple a control signal to the bypass multiplexer before the end of the packet is received by the reception port to initiate a switch between the reception port and the core logic, multiplexer.

10. The memory system of claim 9 further comprising a second memory hub coupled to the reception port, the second memory hub operable to generate data for the upstream link.

11. The memory system of claim 9 further comprising a plurality of memory devices coupled to the core logic.

12. The memory system of claim 9, wherein the breakpoint logic implements a switching algorithm.

13. The memory system of claim 9, wherein the breakpoint logic is operable to determine a type of packet received at the reception port.

14. The memory system of claim 9, wherein the bypass multiplexor is coupled to the reception port through a bypass bus.

15. The memory system of claim 9, further comprising a temporary memory coupled to the reception port and the breakpoint logic, the breakpoint logic further operable to selectively couple the upstream logic to the temporary memory, the temporary memory operable to store data received at the reception port when the reception port is not coupled to the upstream link.

16. The memory system of claim 15, wherein the temporary memory comprises a FIFO memory.

17. The memory system of claim 16, wherein the temporary memory further comprises a data buffer, the data buffer operable to store further data received at the reception port when the FIFO memory is full.

18. The memory system of claim 9, further comprising a clock domain change circuit coupled between the core logic and the bypass multiplexer.

19. A method for controlling communications on an upstream link between a memory module and a memory controller, the method comprising:

coupling the upstream link to a bypass bus of the memory module, the bypass bus being operable to pass upstream data received by the memory module;

determining a local communication is available from a local memory in the memory module, the local memory comprising a local FIFO memory;

identifying a breakpoint in data on the bypass bus;

coupling the upstream link to the local FIFO memory at the breakpoint to couple the local communication to the upstream link if the local communication is available;

storing further upstream data received by the memory module in a temporary FIFO memory while the upstream link is coupled to the local FIFO memory if the temporary FIFO memory is not full; and

storing further upstream data in a second temporary memory when the temporary FIFO memory is full.

20. The method of claim 19, wherein the memory module comprises a bypass multiplexor operable to selectively couple the local memory and the bypass bus to the upstream link, the method further comprising coupling a signal to the bypass multiplexor to begin a switch prior to receiving the breakpoint data on the bypass bus.

21. The method of claim 19, wherein the act of identifying a breakpoint includes identifying a type of packet on the bypass bus.

22. The method of claim 19 wherein the second temporary memory comprises a buffer memory.

23. The method of claim 19 further comprising identifying a second breakpoint after the local communication is coupled to the upstream link, and coupling the upstream link to the temporary memory to receive the further upstream data responsive to detecting the second breakpoint.

24. A memory hub operable to control communications for an upstream link, the memory hub comprising:

a transmission port operable to transmit data to the upstream link;

a reception port operable to receive first data for the upstream link;

core logic operable to receive local data for the upstream link;

a bypass multiplexer coupled to the transmission port, the reception port, and the core logic, the bypass multiplexer operable to selectively couple the upstream link to the reception port or the core logic;

breakpoint logic coupled to the bypass multiplexer operable to identify a breakpoint and, responsive to the identification, operable to couple a control signal to the bypass multiplexer to initiate a switch between the reception port and the core logic;

a temporary FIFO memory coupled to the reception port and the breakpoint logic, the breakpoint logic further operable to selectively couple the upstream logic to the temporary FIFO memory, the temporary FIFO memory operable to store data received at the reception port when the reception port is not coupled to the upstream link; and

a data buffer operable to store further data received at the reception port when the temporary FIFO memory is full.

25. A memory hub operable to control communications for an upstream link, the memory hub comprising:

a transmission port operable to transmit data to the upstream link;

a reception port operable to receive first data for the upstream link;

core logic operable to receive local data for the upstream link;

a bypass multiplexer coupled to the transmission port, the reception port, and the core logic, the bypass multiplexer operable to selectively couple the upstream link to the reception port or the core logic;

breakpoint logic coupled to the bypass multiplexer operable to identify a breakpoint and, responsive to the identification, operable to couple a control signal to the bypass multiplexer to initiate a switch between the reception port and the core logic; and

a clock domain change circuit coupled between the core logic and the bypass multiplexer.

26. A memory system comprising:

a memory controller; and

a memory hub coupled to the controller by an upstream link, the memory hub operable to control communications for the upstream link, the memory hub comprising;

a transmission port coupled to the upstream link;

a reception port operable to receive first data for the upstream link;

core logic operable to receive local data for the upstream link;

a bypass multiplexer coupled to the transmission port, the reception port, and the core logic, the bypass multiplexer operable to selectively couple the upstream link to the reception port or to a local memory;

breakpoint logic coupled to the bypass multiplexer operable to identify a breakpoint and, responsive to the identification, operable to couple a control signal to the bypass multiplexer to initiate a switch between the reception port and the core logic multiplexer;

a temporary FIFO memory coupled to the reception port and the breakpoint logic, the breakpoint logic further operable to selectively couple the upstream logic to the temporary FIFO memory, the temporary FIFO memory operable to store data received at the reception port when the reception port is not coupled to the upstream link; and

a data buffer operable to store further data received at the reception port when the temporary FIFO memory is full.

27. A memory system comprising:

a memory controller; and

a memory hub coupled to the controller by an upstream link, the memory hub operable to control communications for the upstream link, the memory hub comprising;

a transmission port coupled to the upstream link;

a reception port operable to receive first data for the upstream link;

core logic operable to receive local data for the upstream link;

a bypass multiplexer coupled to the transmission port, the reception port, and the core logic, the bypass multiplexer operable to selectively couple the upstream link to the reception port or to a local memory;

breakpoint logic coupled to the bypass multiplexer operable to identify a breakpoint and, responsive to the identification, operable to couple a control signal to the bypass multiplexer to initiate a switch between the reception port and the core logic multiplexer; and

a clock domain change circuit coupled between the core logic and the bypass multiplexer.