System and method for efficient power throttling in multiprocessor chip
First Claim
1. A system for limiting power consumption in a memory attached to a multiprocessor chip comprising:
- a multiprocessor chip;
a plurality of memory controllers inside the multiprocessor chip in communication with a memory, wherein each memory controller includes,a bank counter logic configured to increment a local bank counter in response to a read or write request, the local bank counter indicating how many memory banks are open in the memory by the each memory controller;
total bank counter logic configured to increment a total bank counter value, the total bank counter value indicating a total number of banks open by all the memory controllers;
a time counter logic configured to keep track of time in increments of a set time interval; and
a throttling logic configured to block the read or write request received subsequent to the total bank counter logic reaching a threshold value, the blocking the read or write request including temporarily storing the read or write request, and when terminating the blocking, resuming the read or write requests beginning with the at least one temporarily stored read or write requests;
wherein a signal is sent to the memory controllers to increment the total bank counter values each time a bank is open by any of the memory controllers.
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Accused Products
Abstract
A method for limiting power consumption in a multiprocessor chip is provided. In this method, a read or write request is received by the memory controller, which controls a memory that is external to the multiprocessor chip. The memory controller includes a bank counter that keeps track of the number of read or write requests received by the memory controller. At every clock cycle, the bank counter value is compared with a threshold value to determine whether the counter value is equal to the threshold value. If the bank counter value is determined to be equal to the threshold value, then any subsequent incoming read or write requests are blocked. The bank counter value is incremented each time a read or write request is sent to the memory.
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Citations
19 Claims
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1. A system for limiting power consumption in a memory attached to a multiprocessor chip comprising:
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a multiprocessor chip; a plurality of memory controllers inside the multiprocessor chip in communication with a memory, wherein each memory controller includes, a bank counter logic configured to increment a local bank counter in response to a read or write request, the local bank counter indicating how many memory banks are open in the memory by the each memory controller; total bank counter logic configured to increment a total bank counter value, the total bank counter value indicating a total number of banks open by all the memory controllers; a time counter logic configured to keep track of time in increments of a set time interval; and a throttling logic configured to block the read or write request received subsequent to the total bank counter logic reaching a threshold value, the blocking the read or write request including temporarily storing the read or write request, and when terminating the blocking, resuming the read or write requests beginning with the at least one temporarily stored read or write requests; wherein a signal is sent to the memory controllers to increment the total bank counter values each time a bank is open by any of the memory controllers. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method for limiting power consumption in a multiprocessor chip having integrated memory controllers, the method comprising:
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receiving a read or write request at a particular memory controller, wherein each memory controller has a local bank counter indicating how many memory banks are open in the memory by the each memory controller; incrementing the local bank counter at the particular memory controller; incrementing a total bank counter value at each memory controller, the total bank counter value indicating a total number of banks open by all the memory controllers; and blocking the read or write request received by the particular memory controller subsequent to the total bank counter logic reaching a threshold value, the blocking the read or write request including temporarily storing the read or write request, and when terminating the blocking, resuming the read or write requests beginning with the at least one temporarily stored read or write requests; wherein a signal is sent to the plurality of memory controllers to increment the total bank counter values each time a bank is open by any of the memory controllers. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14)
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15. A computer program embedded in a tangible computer-readable storage medium, when executed by one or more processors, for limiting power consumption in a multiprocessor chip having integrated memory controllers, the computer program comprising:
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program instructions for receiving a read or write request at a particular memory controller, wherein each memory controller has a local bank counter indicating how many memory banks are open in the memory by the each memory controller; program instructions for incrementing the local bank counter at the particular memory controller; program instructions for incrementing a total bank counter value at each memory controller, the total bank counter value indicating a total number of banks open by all the memory controllers; and program instructions for blocking the read or write request received by the particular memory controller subsequent to the total bank counter logic reaching a threshold value, the blocking the read or write request including temporarily storing the read or write request, and when terminating the blocking, resuming the read or write requests beginning with the at least one temporarily stored read or write requests; wherein a signal is sent to the plurality of memory controllers to increment the total bank counter values each time a bank is open by any of the memory controllers. - View Dependent Claims (16, 17, 18, 19)
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Specification