CPU power management based on utilization with lowest performance mode at the mid-utilization range

• US 7,596,709 B2
• Filed: 06/28/2006
• Issued: 09/29/2009
• Est. Priority Date: 12/30/2000
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Cooper, Barnes, Arjangrad, Jalaleddin
• Primary Examiner(s): CHEN, TSE W
• Application Number:
  US11/478,119
• Publication Number:
  US 20070016815A1
• Time in Patent Office: 1,189 Days
• Field of Search: 713/320, 713/323
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A demand-based method and system of a processor power management is described. A processor is caused to enter a particular performance mode based on a first and a second utilization threshold. The particular performance mode includes at least a first performance mode, a second performance mode, and a third performance mode. The processor is caused to operate with a clock frequency in the third performance mode that is lower than the clock frequency of the processor in the first and second performance modes.

Claims

1. A method comprising:

determining a utilization of a processor;

placing the processor in a first performance mode in response to a determination that the utilization is less than or equal to a first utilization threshold;

placing the processor in a second performance mode in response to a determination that the utilization is greater than a second utilization threshold, the first utilization threshold being lower than the second utilization threshold; and

placing the processor in a third performance mode in response to a determination that the utilization is between the first utilization threshold and the second utilization threshold,

wherein placing the processor in the third performance mode includes operating the processor in the first performance mode and operating with a clock frequency that is lower than the clock frequency of the processor in the first and second performance modes.

2. The method of claim 1, wherein a voltage level of the processor is lower in the first performance mode than in the second performance mode.

3. The method of claim 1, wherein a voltage level of the processor is higher in the second performance mode than in the first performance mode and in the third performance mode.

4. The method of claim 1, wherein a voltage level of the processor is also lower in the third performance mode than in the second performance mode.

5. The method of claim 1, further comprising:

placing the processor in a fourth performance mode in response to a determination that the utilization is between the first utilization threshold and a third utilization threshold, the third utilization threshold between the first utilization threshold and the second utilization threshold.

6. The method of claim 5, further comprising:

placing the processor in a fifth performance mode in response to a determination that the utilization is between the second utilization threshold and the third utilization threshold.

7. A computer storage medium having a plurality of instructions executable by a computer system embodied therein, wherein said instructions when executed to cause said computer system to perform the following operations, comprising:

determining a utilization of a central processor;

placing the central processor in a first performance mode in response to a determination that the utilization is less than or equal to a first utilization threshold;

placing the central processor in a second performance mode in response to a determination that the utilization is greater than a second utilization threshold, the first utilization threshold being lower than the second utilization threshold; and

placing the central processor in a third performance mode in response to a determination that the utilization is between the first utilization threshold and the second utilization threshold,

wherein placing the central processor in the third performance mode includes operating the central processor in the first performance mode and operating with a clock frequency that is lower than the clock frequency of the processor in the first and second performance modes.

8. The computer storage medium of claim 7, wherein a voltage level of the central processor is lower in the first performance mode than in the second performance mode.

9. The computer storage medium of claim 7, wherein a voltage level of the central processor is higher in the second performance mode than in the first performance mode and in the third performance mode.

10. The computer storage medium of claim 7, wherein a voltage level of the central processor is also lower in the third performance mode than in the second performance mode.

11. A data processing system comprising:

a central processing unit to process data and execute instructions;

a memory to store a plurality of instructions which when executed by the central processing unit cause the data processing system to;

determining a utilization of the central processing unit;

placing the central processing unit in a first performance mode in response to a determination that the utilization is less than or equal to a first utilization threshold;

placing the central processing unit in a second performance mode in response to a determination that the utilization is greater than a second utilization threshold, the first utilization threshold being lower than the second utilization threshold; and

placing the central processing unit in a third performance mode in response to a determination that the utilization is between the first utilization threshold and the second utilization threshold,

wherein placing the central processing unit in the third performance mode includes operating the central processing unit in the first performance mode and operating with a clock frequency that is lower than the clock frequency of the processor in the first and second performance modes.

12. The data processing system of claim 11, wherein a voltage level of the central processing unit is lower in the first performance mode than in the second performance mode.

13. The data processing system of claim 11, wherein a voltage level of the central processing unit is higher in the second performance mode than in the first performance mode and the third performance mode.

14. The data processing system of claim 11, wherein a voltage level of the central processing unit is also lower in the third performance mode than in the second performance mode.