Apparatus for processing fibre channel and SCSI frames at wire speed

• US 7,596,740 B1
• Filed: 10/27/2003
• Issued: 09/29/2009
• Est. Priority Date: 10/28/2002
• Status: Active Grant

• Current Assignee: NetApp, Inc.
• Original Assignee: NetApp, Inc.
• Inventors: Leong, Reynold, Cuppett, Jeff, Ibrahim, Rahim
• Primary Examiner(s): Lamarre; Guy J
• Application Number:
  US10/695,141
• Time in Patent Office: 2,164 Days
• Field of Search: 714/776
• US Class Current: 714/776
• CPC Class Codes: G06F 2209/509 Offload
• CPC Class Codes: G06F 9/5027 the resource being a machine, e.g. CPUs, Servers, Terminals
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields

Abstract

One or more circuits that validate data frames are provided. The validation may validate information for a fiber channel header and information for a small computer system interface (SCSI) header. The validation is performed by one or more circuits at wire speed.

Claims

1. A circuit configured to process one or more fibre channel and SCSI frames of data, the circuit comprising:

one or more gates corresponding to a number of bits to be validated that validate format information included in a frame of data with simultaneous bit by bit comparisons, wherein error information is written in the frame of data if an error is found in the format information; and

one or more gates corresponding to a number of bits to be validated that validate command information included in the frame of data with simultaneous bit by bit comparisons, wherein error information is written in the frame of data if an error is found in the command information,

wherein the error information for the format information or command information is used in processing a storage operation for the frame of data,

wherein the validation of the format information and command information is performed at wirespeed.

2. The circuit of claim 1, wherein the format information comprises fibre channel format information.

3. The circuit of claim 1, wherein the command information comprises SCSI command information.

4. The circuit of claim 1, wherein the format information comprises at least one of task attributes, task management, and executive management information.

5. The circuit of claim 1, wherein the command information comprises opcode information for the storage operation.

6. The circuit of claim 1, wherein the one or more gates comprise one or more masks that validate the command information.

7. A method for processing fibre channel and SCSI frames of data using an integrated circuit, the method comprising:

receiving a frame of data, the frame of data comprising format information and command information;

determining if the format information is valid performing a simultaneous bit by bit comparison of the format information using one or more gates if the format information is not valid, writing error information indicating an error in the format information in the frame of data;

determining if the command information is valid performing a simultaneous bit by bit comparison of the format information using one or more gates and if the command information is not valid, writing error information indicating an error in the command information in the frame of data,

wherein the error information for the format information or command information is used in processing a storage operation for the frame of data,

wherein determining if the format information valid and determining if the command information is valid is performed at wire speed.

8. The method of claim 7, wherein determining if the format information is valid comprises checking information in the format information using a circuit that performs the determination at wire speed.

9. The method of claim 7, wherein determining if the command information is valid comprises checking information in the command information using a circuit that performs the determination at wire speed.