Method for producing an integrated circuit with a trench transistor structure

• US 7,598,143 B2
• Filed: 09/26/2007
• Issued: 10/06/2009
• Est. Priority Date: 09/26/2006
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Zundel, Markus, Krumrey, Joachim
• Primary Examiner(s): Nguyen; Ha Tran T
• Assistant Examiner(s): Dehne; Aaron A
• Application Number:
  US11/861,900
• Publication Number:
  US 20080076222A1
• Time in Patent Office: 741 Days
• Field of Search: 438/270, 438/542, 438/543, 438545-549, 438/197, 438/133, 438/243, 257/E29.257, 257/E21.418, 257/E21.419, 257/E21.428, 257/E21.429, 257330-342
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for producing an integrated circuit including a semiconductor and in one embodiment a trench transistor structure, is disclosed. A first diffusion method is carried out. A second diffusion method is carried out, by which dopant atoms of a second conduction type are introduced via a first side into a mesa region and into a component region, which form a source zone in the mesa region, the diffusion methods being coordinated with one another in such a way that the dopant atoms of a second conduction type indiffuse further than the dopant atoms of a first conduction type from the first diffusion method, in the vertical direction in the component region and indiffuse not as far as the dopant atoms of the first conduction type in the vertical direction in the mesa region.

Claims

1. A method for producing an integrated circuit including a trench transistor structure comprising:

providing a semiconductor body having a first and a second side and having a cell region;

carrying out a first diffusion method, including introducing dopant atoms of a first conduction type via the first side into a mesa region and into a component region lying outside the cell region, which form a body zone in the mesa region; and

carrying out a second diffusion method, by introducing dopant atoms of a second conduction type into the mesa region and into the component region, which form a source zone in the mesa region, the diffusion methods being coordinated such that the dopant atoms of the second conduction type indiffuse further than the dopant atoms of the first conduction type in a vertical direction in the component region and indiffuse not as far as the dopant atoms of the first conduction type in the vertical direction in the mesa region.

2. The method of claim 1, comprising:

at least two trenches which extend into the semiconductor body proceeding from the first side in a vertical direction, spaced apart from one another in a first lateral direction of the semiconductor body and between which the mesa region is arranged.

3. The method as claimed in claim 1, in which a width of the mesa region in the first lateral direction decreases in the direction of the first side of the semiconductor body.

4. The method of claim 1, in which the first and second diffusion methods in each case comprise an implantation of dopant atoms via the first side into the semiconductor body and a subsequent thermal treatment by using which the implanted dopant atoms indiffuse further.

5. The method of claim 1, comprising wherein the implantation dose for dopant atoms of the first conduction type is between 10¹³ cm⁻

2 and 10¹⁵ cm<sup>−

2</sup>.

6. The method of claim 1, comprising wherein the implantation dose for dopant atoms of the first conduction type is between 10¹⁵ cm⁻

2 and 10¹⁷ cm<sup>−

2</sup>.

7. A method for producing an integrated circuit including a semiconductor having a source zone and a body zone of a trench transistor structure and a component zone having a net doping of the same conduction type as the source zone, comprising:

providing a semiconductor body, including at least two trenches and between which a mesa region is arranged;

carrying out a first diffusion method, by which dopant atoms of a first conduction type are introduced via a first side into the mesa region and into a component region lying outside the cell region; and

carrying out a second diffusion method, by which dopant atoms of a second conduction type are introduced via the first side into the mesa region and into the component region, which form the source zone in the mesa region, the diffusion methods being coordinated with one another in such a way that the dopant atoms of the second conduction type indiffuse further than the dopant atoms of the first conduction type in the vertical direction in the component region.

8. The method of claim 7, comprising wherein the dopant atoms of the second conduction type indiffuse not as far as the dopant atoms of the first conduction type in the vertical direction in the mesa region.

9. The method as claimed in claim 7, in which a width of the mesa region in the first lateral direction decreases in the direction of the first side of the semiconductor body.

10. The method of claim 7, comprising wherein a width of the mesa region is less than 800 nm, and the mesa region adjoins a dielectric in the region of the trenches.

11. The method of claim 10, comprising wherein a width of the mesa region is less than 500 nm.

12. The method of claim 10, comprising wherein the dielectric is an oxide.

13. The method of claim 7, comprising wherein a ratio between a largest width and a smallest width of the mesa region in the first lateral direction is between 1.2 and 10.

14. The method of claim 13, comprising wherein the ratio between a largest width and a smallest width of the mesa region in the first lateral direction is between 1.5 and 5.

15. The method of claim 13, comprising wherein the ratio between a largest width and a smallest width of the mesa region in the first lateral direction is between 1.5 and 2.

16. The method of claim 13, in which the smallest width of the mesa region is between 100 nm and 400 nm.

17. The method of claim 7, in which the first and second diffusion methods in each case comprise an implantation of dopant atoms via the first side into the semiconductor body and a subsequent thermal treatment by using which the implanted dopant atoms indiffuse further.

18. The method of claim 7, comprising wherein the implantation dose for dopant atoms of the first conduction type is between 10¹³ cm⁻

2 and 10¹⁵ cm<sup>−

2</sup>.

19. The method of claim 7, comprising wherein the implantation dose for dopant atoms of the first conduction type is between 10¹⁵ cm⁻

2 and 10¹⁷ cm<sup>−

2</sup>.

20. The method of claim 7, comprising arranging in each case at least one gate electrode in the trenches.

21. The method of claim 20, comprising arranging at least one field electrode in the trenches.

22. The method of claim 7, comprising tapering the mesa region in the direction of the front side in stepped fashion with at least one process in the first lateral direction.

23. The method of claim 7, comprising:

arranging the gate electrode in a manner spaced apart from the first side; and

arranging a section of the mesa region in the first lateral direction between the gate electrodes having a constant width at least in sections.

24. A method for producing an integrated circuit including a source zone and a body zone of a trench transistor structure and a component zone having a net doping of the same conduction type as the source zone, comprising:

providing a semiconductor body having a cell region, in which are arranged at least two trenches, and a mesa region;

carrying out a first diffusion method, which forms the body zone in the mesa region; and

carrying out a second diffusion method, which forms the source zone in the mesa region, the diffusion methods being coordinated with one another in such a way that dopant atoms of the second diffusion method indiffuse further than dopant atoms of the first diffusion method in a vertical direction in the component region, and indiffuse not as far as the dopant atoms of the first diffusion method in the vertical direction in the mesa region.