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Method for forming inter-poly dielectric in shielded gate field effect transistor

  • US 7,598,144 B2
  • Filed: 12/07/2007
  • Issued: 10/06/2009
  • Est. Priority Date: 08/09/2005
  • Status: Active Grant
First Claim
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1. A method of forming a field effect transistor, comprising:

  • forming a trench in a silicon region of a first conductivity type;

    forming a shield electrode in a lower portion of the trench;

    forming an inter-poly dielectric (IPD) comprising a layer of thermal oxide and a layer of conformal dielectric along an upper surface of the shield electrode; and

    forming a gate electrode in the trench over the IPD.

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