SixSnyGe1-x-y and related alloy heterostructures based on Si, Ge and Sn

• US 7,598,513 B2
• Filed: 06/14/2004
• Issued: 10/06/2009
• Est. Priority Date: 06/13/2003
• Status: Expired due to Fees

• Current Assignee: Arizona Board of Regents (University of Arizona)
• Original Assignee: Arizona Board of Regents (University of Arizona)
• Inventors: Kouvetakis, John, Tolle, John, Bauer, Matthew
• Primary Examiner(s): Weiss; Howard
• Assistant Examiner(s): RAO, SHRINIVAS H
• Application Number:
  US10/559,979
• Publication Number:
  US 20060163612A1
• Time in Patent Office: 1,940 Days
• Field of Search: 257/14, 257/15, 257/18, 257/19, 257/200, 257/201, 257/616, 257/E31.035, 257/E33.009, 438/285, 438/936, 117/939, 148/DIG.160, 148/DIG.169, 148/160
• US Class Current: 257/14
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02452 including tin
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02535 including tin
• CPC Class Codes: H01L 21/0259 Microstructure
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 31/028 including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: Y02E 10/547 Monocrystalline silicon PV cells
• CPC Class Codes: Y10S 148/169 Vacuum deposition, e.g. including molecular beam epitaxy
• CPC Class Codes: Y10S 438/936 Graded energy gap

Abstract

A novel method for synthesizing device-quality alloys and ordered phases in a Si—Ge—Sn system uses a UHV-CVD process and reactions of SnD₄ with SiH₃GeH₃. Using the method, single-phase Si_xSn_yGe_1-x-y semiconductors (x≦0.25, y≦0.11) are grown on Si via Ge_1-xSn_x buffer layers The Ge_1-xSn_x buffer layers facilitate heteroepitaxial growth of the Si_xSn_yGe_1-x-y films and act as compliant templates that can conform structurally and absorb the differential strain imposed by the more rigid Si and Si—Ge—Sn materials. The SiH₃GeH₃ species was prepared using a new and high yield method that provided high purity semiconductor grade material.

Claims

1. A semiconductor structure comprising:

a substrate, a Sn_zGe_1-z layer formed over the substrate, and an essentially single-phase Ge_1-x-ySi_xSn_y layer formed over the Sn_zGe_1-z layer.

2. The semiconductor structure of claim 1 wherein the substrate comprises silicon.

4. The structure of claim 1, wherein z is about 0.01 to about 0.05.

5. The structure of claim 1, wherein x is about 0.01 to about 0.25;

and y is about 0.01 to about 0.11.

6. The structure of claim 1, wherein x is about 0.01 to about 0.25;

y is about 0.01 to about 0.11;

z is about 0.01 to about 0.05; and

the substrate comprises silicon.

7. The structure of claim 1, wherein the Ge_1-x-ySi_xSn_y layer is strained.

8. The structure of claim 1, wherein the Ge_1-x-ySi_xSn_y layer is relaxed.

25. The semiconductor structure of claim 1 wherein the Sn_zGe_1-z and Ge_1-x-ySi_xSn_y layers are lattice-matched.

3. A method for synthesizing a compound having the molecular formula H₃Si—

GeH₃, the method comprising combining H₃SiO₃SCF₃ with KGeH₃ under conditions whereby H₃Si—

GeH₃ is obtained.

18. The method of claim 3, wherein the H₃SiO₃SCF₃ and KGeH₃ are combined at about −

60°

C.

9. A method to prepare a semiconductor structure comprising the steps of,

providing a substrate;

depositing a Sn_zGe_1-z layer over the substrate; and

depositing an essentially single-phase Ge_1-x-ySi_xSn_y layer over the Sn_zGe_1-z layer.

10. The method of claim 9, wherein the Ge_1-x-ySi_xSn_y layer is deposited by precursor chemical vapor deposition, wherein the precursor chemical vapor comprises SnD₄ and H₃SiGeH₃.

11. The method of claim 9, wherein the Sn_zGe_1-z layer is deposited by precursor chemical vapor deposition, wherein the precursor chemical vapor comprises SnD₄ and Ge₂H₆.

12. The method of claim 9, wherein the substrate comprises silicon.

13. The method of claim 9, further comprising the step of annealing the Sn_zGe_1-z layer prior to depositing the Ge_1-x-ySi_xSn_y layer.

14. The method of claim 9, wherein z is about 0.01 to about 0.05.

15. The method of claim 9, wherein x is about 0.01 to about 0.25;

and y is about 0.01 to about 0.11.

16. The method of claim 9, wherein x is about 0.01 to about 0.25;

y is about 0.01 to about 0.11;

z is about 0.01 to about 0.05; and

the substrate comprises silicon.

17. The method of claim 9, wherein the Ge_1-x-ySi_xSn_y layer is deposited at a temperature of about 310°

C. to about 375°

C.

19. An alloy of the formula, Ge_1-x-ySi_xSn_y, wherein x is about 0.01 to about 0.25 and y is about 0.01 to about 0.11.

20. The alloy of claim 19, wherein x is about 0.13 to about 0.20.

21. The alloy of claim 20, wherein y is about 0.07 to about 0.11.

22. The alloy of claim 20, wherein y is about 0.01 to about 0.06.

23. A semiconductor structure comprising:

a substrate, a Sn_zGe_1-z layer formed over the substrate, and a layer of an alloy of the formula, Ge_1-x-ySi_xSn_y, wherein x is about 0.01 to about 0.25 and y is about 0.01 to about 0.11 formed over the Sn_zGe_1-z layer.

24. The semiconductor structure of claim 23 wherein the substrate comprises silicon.

26. The semiconductor structure of claim 23 wherein the Sn_zGe_1-z and Ge_1-x-ySi_xSn_y layers are lattice-matched.