Integrated circuit with fuse programming damage detection

• US 7,598,749 B1
• Filed: 06/08/2006
• Issued: 10/06/2009
• Est. Priority Date: 06/08/2006
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Paak, Sunhom, Ang, Boon Yong, Im, Hsung Jai, Pang, Raymond C., Oh, Kwansuhk
• Primary Examiner(s): Nguyen; Vincent Q
• Application Number:
  US11/449,171
• Time in Patent Office: 1,216 Days
• Field of Search: 324/550, 324/555, 324/158.1, 324/765, 324/527, 257/529, 365/225.7
• US Class Current: 324/550
• CPC Class Codes: G01R 31/31717 Interconnect testing by scan techniques see G01R31/31855
• CPC Class Codes: G01R 31/74 Testing of fuses
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/027 in fuses

Abstract

An integrated circuit with an efuse having an efuse link includes a damage detection structure disposed in relation to the efuse so as to detect damage in the IC resulting from programming the efuse. Damage sensing circuitry is optionally included on the IC. Embodiments are used in evaluation wafers to determine proper efuse fabrication and programming parameters, and in production ICs to identify efuse programming damage that might create a latent defect.

Claims

1. An integrated circuit (“

IC”

) comprising;

an efuse having a link; and

a damage detection structure disposed in relation to the efuse so as to detect damage in portions of the IC other than the efuse which result from programming the efuse.

2. The IC of claim 1 wherein the damage detection structure comprises a front-end damage detection structure.

3. The IC of claim 2 wherein the front-end damage detection structure is a field-effect transistor having a well.

4. The IC of claim 3 wherein a portion of the well extends below at least a portion of the link.

5. The IC of claim 2 further comprising a second damage detection structure.

6. The IC of claim 5 wherein the second damage detection structure is a second front-end damage detection structure.

7. The IC of claim 2 wherein the front-end damage detection structure is a P-N device.

8. The IC of claim 1 wherein the damage detection structure comprises a back-end damage detection structure.

9. The IC of claim 8 wherein the back-end damage detection structure comprises a trace.

10. The IC of claim 9 wherein the trace is a first serpentine trace.

11. The IC of claim 10 wherein the back-end damage detection structure further comprises a second trace.

12. The IC of claim 11 wherein the first serpentine trace and the second trace are formed in a first metal layer, and are intertwined, and further comprising a bridge formed in a second metal layer, the bridge connecting a first arm of the first serpentine trace to a second arm of the first serpentine trace.

13. The IC of claim 1 further comprising a damage sensing circuit connected to the damage detection structure.

14. The IC of claim 1 wherein the IC is a field programmable gate array.

15. A method of detecting damage on an integrated circuit (“

IC”

) comprising;

programming an efuse of the IC; and

evaluating an efuse damage detection structure disposed in relation to the efuse so as to detect damage in portions of the IC other than the efuse which result from programming the efuse.

16. The method of claim 15 further comprising evaluating a second efuse damage detection structure disposed in relation to the efuse so as to detect damage in the IC resulting from programming the efuse.

17. The method of claim 16 wherein the efuse damage detection structure is a first front-end efuse damage detection structure and the second efuse damage detection structure is a second front-end efuse damage detection structure.

18. The method of claim 15 wherein the efuse is programmed according to first efuse programming parameters and further comprising a step, after evaluating the efuse damage detection structure, of

programming a second efuse according to second efuse programming parameters;

and

evaluating a second efuse damage detection structure disposed in relation to the second efuse so as to detect damage in the IC resulting from programming the second efuse.

19. A system for detecting damage in an integrated circuit comprising:

means for programming an efuse;

means for detecting efuse programming damage disposed in relation to the efuse so as to detect efuse programming damage in portions of the integrated circuit other than the efuse which result from programming the efuse; and

means for sensing efuse programming damage connected to the means for detecting efuse programming damage.

20. The system of claim 19 wherein the integrated circuit is a field programmable gate array.