Process, supply, and temperature insensitive integrated time reference circuit

• US 7,598,822 B2
• Filed: 04/07/2005
• Issued: 10/06/2009
• Est. Priority Date: 04/07/2005
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Siniscalchi, Patrick Peter, Rajagopal, Narasimhan Trichy
• Primary Examiner(s): Pascal; Robert
• Assistant Examiner(s): Goodley; James E
• Application Number:
  US11/100,783
• Publication Number:
  US 20060226922A1
• Time in Patent Office: 1,643 Days
• Field of Search: 331/111, 331/113.R, 331/143, 331/144, 331/176
• US Class Current: 331/176
• CPC Class Codes: H03K 3/011 Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature to maintain energy constant H03K3/015
• CPC Class Codes: H03K 3/0231 Astable circuits H03K3/0315 takes precedence

Abstract

Precision integrated time reference circuits are disclosed. Preferred embodiments provide time reference circuits that are relatively insensitive to variations in process, supply, and temperature. A preferred embodiment of the invention is disclosed in which a relaxation oscillator according to the invention includes a reference voltage circuit configured to maintain a reference voltage in proportion to actual circuit resistance values. Aspects of the invention also include dynamic compensation for variations in temperature.

Claims

1. A time reference circuit insensitive to internal variations in resistance, capacitance, and temperature, comprising:

an MOS charging capacitor;

a regulated charging current source switchably coupled to the capacitor, the charging current source having an inherent (1/R) resistance variation and having a current proportional to absolute temperature;

a reference voltage circuit for generating a reference voltage that varies as 1/R wherein the resistance variation of the charging current source is compensated for, the reference voltage circuit also having an inherent MOS gate capacitance variation wherein the MOS transistor in the reference voltage circuit substantially compensates for the variation of the MOS charging capacitor; and

wherein the reference voltage circuit has an inherent temperature variation, and wherein the charging current source inherently varies in relationship to the temperature variation of the reference voltage circuit, thereby compensating for the temperature variation.

2. A time reference circuit according to claim 1 described by:

dT={(4*Sc*Cox*R*Rref)/(VPTAT*Up*Cox*S4*(Rp²))}*{1/[1−

Sqrt(S4/S11)²}

where

T=time;

Sc*Cox=Charging capacitor value given by the area of the charging cap (Sc) multiplied by gate capacitance per unit area (Cox);

R=resistance across which a voltage is imposed to create the charging current;

Rp=resistance used in the voltage reference circuit to generate a current (Iref) that varies as (1/Rp)²;

Rref=resistance through which the current Iref sets up the reference voltage Vref;

wherein R, Rp and Rref are all the same type of monolithic resistors such that the process variation in these cancels out;

VPTAT=voltage proportional to absolute temperature;

Up=hole mobility of the voltage generator circuit material;

S4/S11=the relative ratio of switches in the reference voltage generator circuit.

3. A relaxation oscillator circuit comprising:

a charging current generator having a resistance for generating a charging input current from a proportional to absolute temperature voltage making the charging current proportional to absolute temperature;

a reference voltage circuit for generating a reference voltage;

an oscillation generator for receiving the charging current and generating an oscillating output voltage, the oscillation generator further comprising;

one or more MOS capacitors for charging by the charging current;

a comparator circuit configured to compare the voltage across each capacitor to the reference voltage;

a switch circuit controlled by the comparator circuit and coupled to the one or more capacitor for charging and discharging the one or more capacitor;

wherein an untrimmed reference voltage circuit inherently maintains the reference voltage inversely proportional to the charging current generator resistance and proportional to temperature variation and inherent MOS capacitance.

4. A relaxation oscillator circuit according to claim 3 implemented on a single integrated circuit.

5. A relaxation oscillator circuit according to claim 4 further comprising a charging current generator configured for dynamically compensating the charging current for variations in temperature.

6. A monolithic relaxation oscillator circuit with temperature compensation comprising:

a charging current generator having a resistance for generating a charging current from a voltage, the charging current generator configured generating a, charging current proportional to temperature;

a reference voltage circuit for generating a reference voltage proportional to temperature;

an oscillation generator for receiving the charging current and generating an oscillating output voltage, the oscillation generator further comprising;

one or more MOS capacitors for charging by the charging current;

a comparing circuit configured to compare the voltage across each of the one or more capacitors to the reference voltage;

a switch circuit controlled by the comparing circuit and coupled to the one or more MOS capacitors for charging and discharging each of the one or more capacitors;

wherein an untrimmed reference voltage circuit inherently maintains the reference voltage inversely proportional to the charging current generator resistance and proportional to temperature variation and MOS capacitance.

7. A relaxation oscillator circuit according to claim 6 wherein the charging current generator is configured to use a current proportional to absolute temperature for charging the one or more capacitors.

8. A relaxation oscillator circuit according to claim 6 wherein the reference voltage circuit further comprises dual current mirrors for maintaining the reference voltage proportional to charging current generator resistance.

9. A relaxation oscillator circuit according to claim 6 wherein the comparison circuit further comprises dual comparators and dual capacitors.

10. A relaxation oscillator circuit comprising:

means for switching current from an oscillator current source having an inherent 1/R resistance variation and having a current proportional to absolute temperature to obtain a periodic waveform output voltage;

means for generating a reference voltage inversely proportional to the resistance of the oscillator current source wherein the resistance variation is compensated for;

means for comparing the output voltage to the reference voltage; and

untrimmed temperature compensating means for adjusting the oscillator current according to changes in temperature and inherent MOS capacitance, thereby maintaining an output having a substantially fixed frequency.