Nonvolatile memory cell, storage device and nonvolatile logic circuit

• US 7,599,210 B2
• Filed: 08/10/2006
• Issued: 10/06/2009
• Est. Priority Date: 08/19/2005
• Status: Expired due to Fees

• Current Assignee: Sony Semiconductor Solutions Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Okazaki, Nobumichi, Shiimoto, Tsunenori, Otsuka, Wataru, Hachino, Hidenari
• Primary Examiner(s): Le; Vu A
• Assistant Examiner(s): Yang; Han
• Application Number:
  US11/501,697
• Publication Number:
  US 20070041242A1
• Time in Patent Office: 1,153 Days
• Field of Search: 365/185.07, 365/185.08, 365/148, 365/158, 365/163, 365/154, 365/226, 365/171
• US Class Current: 365/148
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 14/009 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 2013/0073 Write using bi-directional cell biasing

Abstract

One or serially connected field effect transistors are cross coupled with each other, first terminals of nonvolatile variable resistance elements are connected to their storage nodes, and the other terminals of the variable resistance elements are connected to a power supply line to thereby form a memory cell. By controlling the voltage supplied to this power supply line, data of the memory cell immediately before turning off the power is stored in it when the power is turned off.

Claims

1. A memory cell comprising:

a pair of inverters including a pair of field effect transistors and a pair of nonvolatile variable resistance elements connected to drain terminals of the transistors and having cross-coupled input/output terminals; and

a power supply line connected to other terminals of the nonvolatile variable resistance elements and supplied with a control voltage, said control voltage controlling data storage within the memory cell when power to said memory cell is turned off.

2. The memory cell as set forth in claim 1, wherein the nonvolatile variable resistance elements perform a write or erase operation by voltages of different polarities being applied to the two terminals of the variable resistance elements.

3. A memory cell comprising:

a cross coupled pair of inverters including N-channel field effect transistors and P-channel field effect transistors serially connected, a pair of nonvolatile variable resistance elements connected to storage nodes of the cross coupled pair of inverters, and

a power supply line connected to first terminals of the nonvolatile variable resistance elements and to which a control voltage is supplied, said control voltage controlling data storage within the memory cell when power to said memory cell is turned off.

4. The memory cell as set forth in claim 3, wherein the nonvolatile variable resistance elements perform a write or erase operation by being supplied with voltages of different polarities at their two terminals.

5. A storage device comprising:

memory cells, each having a pair of inverters including a pair of field effect transistors and a pair of nonvolatile variable resistance element connected to drain terminals of the transistors and having cross-coupled input/output terminals and a power supply line connected to other terminals of the nonvolatile variable resistance elements and supplied with a control voltage, arranged in a matrix, a word line commonly connecting gate terminals of access transistors of the memory cells in a row direction, a pair of bit lines commonly connecting drain terminals of the access transistors in a column direction, and a control circuit supplying a control voltage to the power supply line commonly connected to first terminals of the variable resistance elements for changing characteristics of the variable resistance elements,

wherein said control voltage controls data storage within the memory cell when power to said memory cell is turned off.

6. The storage device as set forth in claim 5, wherein the nonvolatile variable resistance elements perform a write or erase operation by being supplied with voltages of different polarities at their two terminals.

7. The storage device as set forth in claim 5, wherein the control circuit supplies the power supply line with a pulse of a first reference voltage when performing a write operation, a erase operation, or a read operation on the memory cells and sets it to a second reference voltage other than when performing a write operation on the memory cells.

8. The storage device as set forth in claim 5, wherein the control circuit performs a write or erase operation on nonvolatile variable resistance elements in the memory cells by making the word lines a high potential to conduct the access transistors conductive and, in that state, setting the power supply line at a high potential to erase information of the nonvolatile variable resistance elements in the memory cells, then, while leaving the access transistors conductive, setting the power supply line at a low potential to write in the nonvolatile variable resistance elements in the memory cells and performs a read operation on the memory cells by setting the word lines at a low potential to close the access transistors and, in that state, setting the power supply line at a high potential to transfer information from the nonvolatile variable resistance elements to memory cell storage nodes, and then setting the word lines at a high potential to conduct the access transistors and read information of the memory cells.

9. The storage device as set forth in claim 5, wherein the control circuit supplies the power supply line with a pulse of the first reference voltage when performing a write operation on the memory cells and sets it to a second reference voltage other than when performing a write operation on the memory cells.

10. The storage device as set forth in claim 9, wherein the control circuit performs a write or erase operation on nonvolatile variable resistance elements in the memory cells by setting the word lines at a high potential to conduct access transistors conductive and, in that state, setting the power supply line at a high potential to erase information of the nonvolatile variable resistance elements in the memory cells, and then, while leaving the access transistors conductive, setting the power supply line at a low potential to write in the nonvolatile variable resistance elements in the memory cells.

11. The storage device as set forth in claim 9, wherein when turning on the power, in the state where access transistors of the memory cells are closed, the control circuit changes the power supply line to a high potential before the power supplies of the memory cells so as to transfer information stored in the nonvolatile variable resistance elements to storage nodes of the memory cells.

12. A storage device comprising:

memory cells, each having a cross coupled pair of inverters including N-channel field effect transistors and P-channel field effect transistors serially connected, a pair of;

nonvolatile variable resistance elements connected to storage nodes of the cross coupled pair of inverters, and a power supply line connected to first ends of the nonvolatile variable resistance, arranged in a matrix, a word line commonly connecting gate terminals of access transistors of the memory cells in a row direction, a pair of bit lines commonly connecting drain terminals of the access transistors in a column direction, and a control circuit supplying a control voltage to the power supply line commonly connected to first ends of the variable resistance elements for changing characteristics of the variable resistance elements,

wherein said control voltage controls data storage within the memory cell when power to said memory cell is turned off.

13. The storage device as set forth in claim 12, wherein the nonvolatile variable resistance elements perform a write or erase operation by being supplied with voltages of different polarities at their two terminals.

14. The storage device as set forth in claim 12, wherein the control circuit supplies the power supply line with a pulse of a first reference voltage when performing a write operation on the memory cells and sets it to a second reference voltage other than when performing a write operation on the memory cells.

15. The storage device as set forth in claim 14, wherein the control circuit performs a write or erase operation on nonvolatile variable resistance elements in the memory cells by setting the word lines at a high potential to conduct access transistors and, in that state, setting the power supply line at a high potential to erase information of the nonvolatile variable resistance elements in the memory cells, and then, while leaving the access transistors conductive, setting the power supply line at a low potential to write in the nonvolatile variable resistance elements in the memory cells.

16. The storage device as set forth in claim 14, wherein when turning on the power, in the state where access transistors of the memory cells are closed, the control circuit changes the power supply line to a high potential before the power supplies of the memory cells so as to transfer information stored in the nonvolatile variable resistance elements to storage nodes of the memory cells.

17. The storage device as set forth in claim 12, wherein while the power supplies of the memory cells are at a normal power potential immediately before the power is turned off, the control circuit changes the power supply line to a low potential so as to write information of storage nodes of the memory cells in the nonvolatile variable resistance elements.

18. The storage device as set forth in claim 17, wherein when turning on the power, in the state where access transistors of the memory cells are closed, the control circuit changes the power supply line to a high potential before the power supplies of the memory cells so as to transfer information stored in the nonvolatile variable resistance elements to storage nodes of the memory cells.

19. A nonvolatile logic circuit comprising:

a flip-flop circuit including a pair of inverters with output terminals cross coupled with each other'"'"'s input terminals, and an additional circuit having a pair of nonvolatile variable resistance elements with first terminals connected to storage nodes of the flip-flop circuit and a second power supply line to which other terminals of the nonvolatile variable resistance elements are connected and provided separate from a first power supply line of the inverters to which a control voltage is supplied and driving the second power supply line by the control voltage so as to store data of the flip-flop circuit in the nonvolatile variable resistance elements when the first power supply line is turned off,

wherein said control voltage controlling data storage within the memory cell when power to said memory cell is turned off.

20. The nonvolatile logic circuit as set forth in claim 19, wherein the nonvolatile variable resistance elements perform a write or erase operation by being supplied with voltages of different polarities at their two terminals.