Dynamic reconfiguration of a system monitor (DRPORT)

• US 7,599,299 B2
• Filed: 04/30/2004
• Issued: 10/06/2009
• Est. Priority Date: 04/30/2004
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: McGrath, John, Collins, Anthony J., Goetting, F. Erich
• Primary Examiner(s): Pham; Chi H
• Assistant Examiner(s): Faroul; Farah
• Application Number:
  US10/837,330
• Publication Number:
  US 20050262492A1
• Time in Patent Office: 1,985 Days
• Field of Search: 370/241, 370/537, 370/254, 327/254, 327/379, 709/224
• US Class Current: 370/241
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals

Abstract

Method and apparatus for a dynamically reconfigurable system monitor (20) are described. A system monitor (20) has registers (206) accessible via a reconfiguration port (201). At least one of the registers may be dynamically reconfigured via the reconfiguration port (201) to select a channel to be monitored or to store an alarm value to be used in monitoring by the system monitor (20). Additionally, the system monitor (20) may be embedded in a columnar block architecture.

Claims

1. A method of system monitoring, comprising:

providing a system monitor having registers accessible via a reconfiguration port; and

dynamically reconfiguring at least one of the registers via the reconfiguration port to select a channel to be monitored by the system monitor;

the system monitor including an analog-to-digital converter;

wherein the dynamically reconfiguring is performed while operating the analog-to-digital converter.

2. The method, according to claim 1, wherein the channel is selected by providing a channel select signal to a multiplexer.

3. The method, according to claim 2, wherein the multiplexer output is coupled to an analog-to-digital converter input of the analog-to-digital converter.

4. The method, according to claim 3, wherein the at least one register is a dual ported memory, the dual ported memory being configuration memory of a programmable logic device.

5. The method, according to claim 3, wherein the at least one register is a random access memory, the random access memory being block memory of a programmable logic device.

6. The method, according to claim 5, further comprising setting default values for the system monitor responsive to a configuration bit stream used to initialize the programmable logic device.