Binary polynomial multiplier
First Claim
1. A programmable CPU multiplier responsive to instructions dedicated to polynomial operations, comprising:
- an array unit responsive to instructions dedicated to polynomial operations, the array unit having;
a first array that is used to perform arithmetic multiplication, the first array having a first result output and a second result output; and
a second array that is used to perform binary polynomial multiplication, the second array having a third result output; and
a carry propagation adder having a first input, a second input, and an output, whereinthe first input of the carry propagation adder is selectively coupled to the first result output of the first array,the second input of the carry propagation adder is selectively coupled to the second result output of the first array and the third result output of the second array, andthe output of the carry propagation adder is stored in a register to provide an output of the polynomial operations.
5 Assignments
0 Petitions
Accused Products
Abstract
A multiply unit includes support for arithmetic operations, binary polynomial operations, and permutations. To this end, the multiply unit may include an input data path that receives input operands, an arithmetic multiplier connected to receive the input operands, a binary polynomial multiplier having components separate and distinct from the arithmetic multiplier and connected to receive the one or more input operands, and a multiply unit output data path connected to receive an output of the arithmetic multiplier and connected to receive an output of the binary polynomial multiplier. The multiply unit also may include permutation logic that performs permutation operations on the input operands.
219 Citations
39 Claims
-
1. A programmable CPU multiplier responsive to instructions dedicated to polynomial operations, comprising:
-
an array unit responsive to instructions dedicated to polynomial operations, the array unit having; a first array that is used to perform arithmetic multiplication, the first array having a first result output and a second result output; and a second array that is used to perform binary polynomial multiplication, the second array having a third result output; and a carry propagation adder having a first input, a second input, and an output, wherein the first input of the carry propagation adder is selectively coupled to the first result output of the first array, the second input of the carry propagation adder is selectively coupled to the second result output of the first array and the third result output of the second array, and the output of the carry propagation adder is stored in a register to provide an output of the polynomial operations. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
-
-
13. A tangible computer-readable storage medium comprising a programmable CPU multiplier responsive to instructions dedicated to polynomial operations embodied in software, the programmable CPU multiplier comprising:
-
an array unit responsive to instructions dedicated to polynomial operations, the array unit having; a first array that is used to perform arithmetic multiplication, the first array having a first result output and a second result output; and a second array that is used to perform binary polynomial multiplication, the second array having a third result output; and a carry propagation adder having a first input, a second input, and an output, wherein the first input of the carry propagation adder is selectively coupled to the first result output of the first array, the second input of the carry propagation adder is selectively coupled to the second result output of the first array and the third result output of the second array, and the output of the carry propagation adder is stored in a register to provide an output of the polynomial operations. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
-
-
27. A system, comprising:
-
a processor for performing multiplication, the processor including; an execution unit responsive to a first set of instructions, and a multiply-divide unit, responsive to a second set of instructions dedicated to polynomial operations, the multiply-divide unit comprising; an array unit in the processor for performing multiplication having; a first array that is used to perform arithmetic multiplication, the first array having a first result output and a second result output, and a second array that is used to perform binary polynomial multiplication, the second array having a third result output, and a carry propagation adder having a first input, a second input, and an output, wherein the first input of the carry propagation adder is selectively coupled to the first result output of the first array, the second input of the carry propagation adder is selectively coupled to the second result output of the first array and the third result output of the second array, and the output of the carry propagation adder is stored in a register to provide an output of the polynomial operations; and a memory coupled to the processor to store the first and second set of instructions. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39)
-
Specification