Recovering from a failed I/O controller in an information handling system

• US 7,600,157 B2
• Filed: 10/14/2008
• Issued: 10/06/2009
• Est. Priority Date: 01/23/2003
• Status: Expired due to Term

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: McAfee, Martin, Vasudevan, Bharath
• Primary Examiner(s): Beausoliel; Robert
• Assistant Examiner(s): Mehrmanesh; Elmira
• Application Number:
  US12/250,847
• Publication Number:
  US 20090037776A1
• Time in Patent Office: 357 Days
• Field of Search: 714/3, 714/5, 714/43
• US Class Current: 714/43
• CPC Class Codes: G06F 11/2017 where memory access, memory control or I/O control functionality is redundant redundant communication control functionality G06F11/2005; redundant storage control functionality G06F11/2089

Abstract

An information handling system includes first and second input/output (I/O) controllers, a detector for detecting an I/O controller failure, and an I/O recovery unit. The first I/O controller adaptively controls a first and a second I/O slot. The second I/O controller adaptively controls a third and a fourth I/O slot. Lastly, the I/O recovery unit, responsive to a detected I/O controller failure, operatively couples/decouples the first and second I/O slot to/from the first I/O controller, operatively couples/decouples the third and fourth I/O slot to/from the second I/O controller, and operatively decouples/couples the first and second I/O slot from/to the third and fourth I/O slot according to an I/O failure recovery protocol, the I/O failure recovery protocol provided for adapting one of either the first and second I/O controllers to operatively couple to the first, second, third and fourth I/O slots as a function of the detected I/O controller failure.

Claims

1. An information handling system (IHS) comprising:

a first input/output (I/O) controller adapted to control a first and a second I/O slot in a normal operation state;

a second I/O controller adapted to control a third and a fourth I/O slot in a normal operation state;

means including a power on self test (POST) routine for detecting an I/O controller failure;

switching means, responsive to a detected I/O controller failure, for operatively coupling/decoupling the first and second I/O slot to/from the first I/O controller, for operatively coupling/decoupling the third and fourth I/O slot to/from the second I/O controller, and for operatively decoupling/coupling the first and second I/O slot from/to the third and fourth I/O slot according to an I/O failure recovery protocol, the I/O failure recovery protocol being provided for adapting one of either the first and second I/O controllers to operatively couple to the first, second, third and fourth I/O slots as a function of the detected I/O controller failure, wherein the first and second I/O controllers include PCI controllers and the first, second, third, and fourth I/O slots each include a PCI slot;

the switching means provided to couple the first, second, third, and fourth I/O slots to one of the first and the second I/O controllers; and

one of the first and second I/O controllers provided to control the first, second, third, and fourth I/O slots, wherein the one of the first and second I/O controllers is set to half bus speed.

2. The IHS of claim 1, wherein said first I/O controller includes an I/O bus speed strapping input configured to control a bus speed of a first I/O bus, wherein said second I/O controller includes an I/O bus speed strapping input configured to control a bus speed of a second I/O bus, and wherein the I/O failure recovery protocol further operates to control the I/O bus speed of the first, second, third and fourth I/O slots as a function of the detected I/O controller failure and one of the I/O bus speed strapping inputs of said first and second I/O controllers.

3. The IHS of claim 1, wherein the POST routine includes executable code for an implementing an auto-bus scan, the auto-bus scan being provided for scanning the I/O controllers and switches to learn all permutations of failures and store the learned permutations.

4. The IHS of claim 3, wherein responsive to a detection of an I/O controller failure, the POST routine executes a permutation to recover from the I/O controller failure.

5. The IHS of claim 4, wherein said means for operatively coupling/decoupling the first and second I/O slot to/from said first I/O controller, for operatively coupling/decoupling the third and fourth I/O slot to/from said second I/O controller, and for operatively decoupling/coupling the first and second I/O slot from/to the third and fourth I/O slot according to an I/O failure recovery protocol includes first, second and third switches, respectively.

6. The IHS of claim 5, further wherein the POST routine instructs the first, second, and third switches to open/close via at least one selected from the group consisting of a GPIO output and a PLD output.

7. The IHS of claim 1, wherein said means for operatively coupling/decoupling the first and second I/O slot to/from said first I/O controller, for operatively coupling/decoupling the third and fourth I/O slot to/from said second I/O controller, and for operatively decoupling/coupling the first and second I/O slot from/to the third and fourth I/O slot according to an I/O failure recovery protocol includes first, second and third switches, respectively.

8. The IHS of claim 7, wherein the first switch includes a switch control input, wherein responsive to a first input, the first switch operates to couple the first and second I/O slot to said first I/O controller and wherein responsive to a second input, the first switch operates to decouple the first and second I/O slot from said first I/O controller.

9. The IHS of claim 7, wherein the second switch includes a switch control input, wherein responsive to a first input, the second switch operates to couple the third and fourth I/O slot to said second I/O controller and wherein responsive to a second input, the second switch operates to decouple the third and fourth I/O slot from said first I/O controller.

10. The IHS of claim 7, wherein the third switch includes a switch control input, wherein responsive to a first input, the third switch operates to decouple the first and second I/O slots from the third and fourth I/O slots and wherein responsive to a second input, the third switch operates to couple the first and second I/O slots to the third and fourth I/O slots.