Iterative metric updating when decoding LDPC (low density parity check) coded signals and LDPC coded modulation signals

• US 7,600,180 B2
• Filed: 01/03/2007
• Issued: 10/06/2009
• Est. Priority Date: 06/13/2003
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Shen, Ba-Zhong, Tran, Hau Thien, Cameron, Kelly Brian
• Primary Examiner(s): Lamarre; Guy J
• Assistant Examiner(s): RIZK, SAMIR WADIE
• Application Number:
  US11/648,958
• Publication Number:
  US 20070124644A1
• Time in Patent Office: 1,007 Days
• Field of Search: 714/801, 714/752, 714/758
• US Class Current: 714/801
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/1105 Decoding
• CPC Class Codes: H03M 13/1117 using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the min-sum rule
• CPC Class Codes: H03M 13/25 Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] modulation codes H03M13/31
• CPC Class Codes: H03M 13/255 with Low Density Parity Check [LDPC] codes
• CPC Class Codes: H03M 13/256 with trellis coding, e.g. with convolutional codes and TCM
• CPC Class Codes: H03M 13/258 with turbo codes, e.g. Turbo Trellis Coded Modulation [TTCM]
• CPC Class Codes: H03M 13/2957 Turbo codes and decoding
• CPC Class Codes: H03M 13/4161 implementing path management
• CPC Class Codes: H03M 13/45 Soft decoding, i.e. using symbol reliability information H03M13/41 takes precedence
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/005 Iterative decoding, including iteration between signal detection and decoding operation
• CPC Class Codes: H04L 1/0058 Block-coded modulation
• CPC Class Codes: H04L 1/006 Trellis-coded modulation
• CPC Class Codes: H04L 27/18 Phase-modulated carrier systems, i.e. using phase-shift keying H04L27/32 takes precedence
• CPC Class Codes: H04L 27/2602 Signal structure

Abstract

Iterative metric updating when decoding LDPC (Low Density Parity Check) coded signals and LDPC coded modulation signals. A novel approach is presented for updating the bit metrics employed when performing iterative decoding of LDPC coded signals. This bit metric updating is also applicable to decoding of signals that have been generated using combined LDPC coding and modulation encoding to generate LDPC coded modulation signals. In addition, the bit metric updating is also extendible to decoding of LDPC variable code rate and/or variable modulation signals whose code rate and/or modulation may vary as frequently as on a symbol by symbol basis. By ensuring that the bit metrics are updated during the various iterations of the iterative decoding processing, a higher performance can be achieved than when the bit metrics remain as fixed values during the iterative decoding processing.

Claims

1. A method for operating a decoder to decode an LDPC (Low Density Parity Check) coded signal, the method comprising:

employing a bit node processing module and a check node processing module to perform bit node processing and check node processing, respectively, during a first decoding iteration in which the bit node processing employs a first plurality of bit metrics and the decoder generates a first soft estimate of a bit within the LDPC coded signal, wherein the plurality of bit metrics corresponds to a bit within the LDPC coded signal;

updating the first plurality of bit metrics using the first soft estimate thereby generating a second plurality of bit metrics; and

employing the bit node processing module and the check node processing module to perform bit node processing and check node processing, respectively, during a second decoding iteration in which the bit node processing employs the second plurality of bit metrics and the decoder generates a second soft estimate of the bit within the LDPC coded signal.

2. The method of claim 1, further comprising:

hard limiting the second soft estimate of the bit within the LDPC coded signal thereby making a best estimate of the bit within the LDPC coded signal.

3. The method of claim 1, further comprising:

receiving the LDPC coded signal from a communication channel;

processing the LDPC coded signal thereby generating a plurality of symbol metrics that corresponds to a symbol within the LDPC coded signal; and

processing the plurality of symbol metrics thereby generating the first plurality of bit metrics that corresponds to the bit within the LDPC coded signal.

4. The method of claim 1, wherein:

the first decoding iteration includes;

updating a first plurality of bit edge messages using the first plurality of bit metrics thereby generating a second plurality of bit edge messages;

updating a first plurality of check edge messages using the second plurality of bit edge messages thereby generating a second plurality of check edge messages; and

computing the first soft estimate of the bit within the LDPC coded signal using the second plurality of check edge messages; and

the second decoding iteration includes;

updating the second plurality of bit edge messages using the second plurality of bit metrics thereby generating a third plurality of bit edge messages;

updating the second plurality of check edge messages using the third plurality of bit edge messages thereby generating a third plurality of check edge messages; and

computing the second soft estimate of the bit within the LDPC coded signal using the second plurality of check edge messages.

5. The method of claim 1, further comprising:

initializing a plurality of bit edge messages using the first plurality of bit metrics.

6. The method of claim 1, wherein:

the LDPC coded signal includes a first LDPC coded symbol and a second LDPC coded symbol;

the first LDPC coded symbol is symbol mapped to a first constellation whose constellation points have a first mapping; and

the second LDPC coded symbol is symbol mapped to a second constellation whose constellation points have a second mapping.

7. The method of claim 1, wherein:

the LDPC coded signal includes a first LDPC coded symbol and a second LDPC coded symbol;

the first LDPC coded symbol is symbol mapped to a constellation when its constellation points have a first mapping; and

the second LDPC coded symbol is symbol mapped to the constellation when its constellation points have a second mapping.

8. The method of claim 1, wherein:

the LDPC coded signal includes a first LDPC coded symbol and a second LDPC coded symbol;

the first LDPC coded symbol is LDPC encoded according to a first code rate; and

the second LDPC coded symbol is LDPC encoded according to a second code rate.

9. The method of claim 1, wherein:

the method is performed within a communication device; and

the communication device is implemented within a wireless communication system.

10. The method of claim 1, wherein:

the decoder is implemented within a communication device; and

the communication device is implemented within at least one of a satellite communication system, an HDTV (High Definition Television) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, a fiber-optic communication system, a WLAN (Wireless Local Area Network) communication system, and a DSL (Digital Subscriber Line) communication system.

11. A method for operating a decoder to decode an LDPC (Low Density Parity Check) coded signal, the method comprising:

during a first decoding iteration;

employing a bit node processing module to perform bit node processing that involves using a first plurality of bit metrics when updating a first plurality of bit messages thereby generating a second plurality of bit edge messages, wherein the first plurality of bit metrics corresponds to a bit within the LDPC coded signal;

employing a check node processing module to perform check node processing that involves using the second plurality of bit edge messages when updating a first plurality of check edge messages thereby generating a second plurality of check edge messages; and

computing a first soft estimate of the bit within the LDPC coded signal using the second plurality of check edge messages; and

during a second decoding iteration;

updating the first plurality of bit metrics using the soft estimate thereby generating a second plurality of bit metrics;

employing the bit node processing module to perform bit node processing that involves using the second plurality of bit metrics when updating the second plurality of bit messages thereby generating a third plurality of bit edge messages;

employing the check node processing module to perform check node processing that involves using the third plurality of bit edge messages when updating the second plurality of check edge messages thereby generating a third plurality of check edge messages; and

computing a second soft estimate of the bit within the LDPC coded signal using the third plurality of check edge messages.

12. The method of claim 11, further comprising:

hard limiting the second soft estimate of the bit within the LDPC coded signal thereby making a best estimate of the bit within the LDPC coded signal.

13. The method of claim 11, further comprising:

receiving the LDPC coded signal from a communication channel;

processing the LDPC coded signal thereby generating a plurality of symbol metrics that corresponds to a symbol within the LDPC coded signal; and

processing the plurality of symbol metrics thereby generating the first plurality of bit metrics that corresponds to the bit within the LDPC coded signal.

14. The method of claim 11, wherein:

the LDPC coded signal includes a first LDPC coded symbol and a second LDPC coded symbol;

the first LDPC coded symbol is symbol mapped to a first constellation whose constellation points have a first mapping; and

the second LDPC coded symbol is symbol mapped to a second constellation whose constellation points have a second mapping.

15. The method of claim 11, wherein:

the LDPC coded signal includes a first LDPC coded symbol and a second LDPC coded symbol;

the first LDPC coded symbol is LDPC encoded according to a first code rate; and

the second LDPC coded symbol is LDPC encoded according to a second code rate.

16. The method of claim 11, wherein:

the method is performed within a communication device; and

the communication device is implemented within a wireless communication system.

17. A decoder that is operable to decode an LDPC (Low Density Parity Check) coded signal, the decoder comprising:

a bit node processing module that is operable to employ a first plurality of bit metrics when updating a first plurality of bit edge messages thereby generating a second plurality of bit edge messages, wherein the plurality of bit metrics corresponds to a bit within the LDPC coded signal; and

a check node processing module that is operable to employ the second plurality of bit edge messages when updating a first plurality of check edge messages thereby generating a second plurality of check edge messages; and

wherein;

the bit node processing module is operable to process the second plurality of check edge messages thereby generating a first soft estimate of the bit within the LDPC coded signal;

the decoder is operable to update the first plurality of bit metrics using the first soft estimate thereby generating a second plurality of bit metrics;

the bit node processing module is operable to employ the second plurality of bit metrics when updating the second plurality of bit edge messages thereby generating a third plurality of bit edge messages;

the check node processing module is operable to employ the third plurality of bit edge messages when updating the second plurality of check edge messages thereby generating a third plurality of check edge messages; and

the bit node processing module is operable to process the third plurality of check edge messages thereby generating a second soft estimate of the bit within the LDPC coded signal.

18. The decoder of claim 17, further comprising:

a hard limiter that is operable to process the second soft estimate of the bit within the LDPC coded signal thereby making a best estimate of the bit within the LDPC coded signal.

19. The decoder of claim 17, wherein:

the LDPC coded signal includes a first LDPC coded symbol and a second LDPC coded symbol;

the first LDPC coded symbol is symbol mapped to a first constellation whose constellation points have a first mapping; and

the second LDPC coded symbol is symbol mapped to a second constellation whose constellation points have a second mapping.

20. The decoder of claim 17, wherein:

the LDPC coded signal includes a first LDPC coded symbol and a second LDPC coded symbol;

the first LDPC coded symbol is LDPC encoded according to a first code rate; and

the second LDPC coded symbol is LDPC encoded according to a second code rate.